公开(公告)号：US20240381603A1

公开(公告)日：2024-11-14

申请号：US18316813

申请日：2023-05-12

Applicant: NOKIA SOLUTIONS AND NETWORKS OY

Inventor： Paul Brown ,  Alex Chan

IPC: H05K13/04 ,  G06F30/392 ,  H05K13/08

Abstract: A system and method for matching a plurality of components to a plurality of printed circuit board (PCB), including: characterizing the warpage characteristics of the plurality of components; characterizing the warpage characteristics of a site of the plurality of PCBs where the component will be placed; determining viable component and PCB pairings based upon the component warpage characteristics and the PCB warpage characteristics; and assembling the pairs of components and PCBs.

公开(公告)号：US20250031318A1

公开(公告)日：2025-01-23

申请号：US18354907

申请日：2023-07-19

Applicant: NOKIA SOLUTIONS AND NETWORKS OY

Inventor： Paul Brown ,  Alex Chan

IPC: H05K3/42 ,  H05K1/11 ,  H05K3/00

Abstract: A method of manufacturing a via-in-via vertical interconnect in a printed circuit board (PCB), including: drilling a first hole through the PCB; drilling a second hole into a top side of the PCB; plating the first hole and the second hole with a conductive material to form an outer layer; drilling a third hole through the PCB wherein a portion of the plating is removed between the first hole and the second hole; filling the first, second, and third holes with an outer filler; drilling a fourth hole through the outer filler; plating the fourth hole with a conductive material to form an inner layer; filling the fourth hole with an inner filler; forming a via-in-via pad on top of the inner filler connected to the inner layer; and drilling a fifth hole through the bottom of the PCB along the fourth hole to remove a portion of the inner filler and inner layer wherein the top of the fifth hole is below the internal layer.

公开(公告)号：US20240347432A1

公开(公告)日：2024-10-17

申请号：US18298645

申请日：2023-04-11

Applicant: Nokia Solutions and Networks Oy

Inventor： Alex Chan ,  Paul Brown ,  Daniel Fazari

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49816 ,  H01L23/3128 ,  H01L23/49827 ,  H01L24/16 ,  H01L24/26 ,  H01L2224/16221 ,  H01L2924/15311 ,  H01L2924/3511

Abstract: A circuit assembly, including: an integrated circuit (IC) with a plurality of connection pads; a ball grid array (BGA) including a plurality of solder balls arranged in an array, where plurality of solder balls are configured to connect the plurality of connections pads to a plurality of connections pads on a PCB; and a BGA spacer configured to fit among the plurality of solder balls, wherein the BGA spacer has a width based upon a height and spacing of the plurality of solder balls and a height based upon a height and spacing of the plurality of solder balls and a minimum distance between the IC and the PCB to prevent shorting of adjacent solder balls.

公开(公告)号：US10667399B1

公开(公告)日：2020-05-26

申请号：US16201362

申请日：2018-11-27

Applicant: NOKIA SOLUTIONS AND NETWORKS OY

Inventor： Alex Chan ,  Paul Brown

IPC: H05K1/00 ,  H05K1/11 ,  H05K1/18 ,  H01L21/02 ,  H01L21/56 ,  H01L23/02 ,  H01L23/48 ,  H01L23/66 ,  H01L23/367 ,  H01L23/495 ,  H01L23/538 ,  H01L23/552 ,  H05K1/14

Abstract: A printed circuit board (PCB) carrier including a multi-layer structure including a plurality of conductive layers and a plurality of insulating layers respectively spaced between the plurality of conductive layers, the multi-layer structure having a footprint corresponding to a large size component of the PCB, and a pocket formed in the multi-layer structure, the pocket configured to receive a discrete component of a size smaller than the large size component.