公开(公告)号：US09716051B2

公开(公告)日：2017-07-25

申请号：US13668077

申请日：2012-11-02

Applicant: NVIDIA CORPORATION

Inventor： Leilei Zhang ,  Ron Boja ,  Abraham Yee ,  Zuhair Bokharey

IPC: H01L23/495 ,  H01L23/52 ,  H01L23/31 ,  H01L23/42 ,  H01L23/00 ,  H05K1/02 ,  H01L23/498 ,  H05K3/46

CPC classification number: H01L23/3128 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/16 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/3512 ,  H05K1/0271 ,  H05K3/4644 ,  H05K2201/09136 ,  H05K2201/2009 ,  H01L2224/05599

Abstract: A packaging substrate, a packaged semiconductor device, a computing device and methods for forming the same are provided. In one embodiment, a packaging substrate is provided that includes a packaging structure having a chip mounting surface and a bottom surface. The packaging structure has at a plurality of conductive paths formed between the chip mounting surface and the bottom surface. The conductive paths are configured to provide electrical connection between an integrated circuit chip disposed on the chip mounting surface and the bottom surface of the packaging structure. The packaging structure has an opening formed in the chip mounting surface proximate a perimeter of the packaging structure. A stiffening microstructure is disposed in the opening and is coupled to the packaging structure.

公开(公告)号：US09368422B2

公开(公告)日：2016-06-14

申请号：US13722603

申请日：2012-12-20

Applicant: NVIDIA CORPORATION

Inventor： Leilei Zhang ,  Ron Boja ,  Abraham F. Yee ,  Zuhair Bokharey

IPC: H01L23/12 ,  H01L23/48 ,  H01L29/40 ,  H01L23/31 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L23/31 ,  H01L21/563 ,  H01L24/32 ,  H01L2224/16225 ,  H01L2224/27013 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/00

Abstract: One embodiment sets forth an integrated circuit package that includes a substrate, one or more devices mounted on the substrate, a layer of under-fill configured to secure the one or more devices on the substrate, and a solder trench formed in the substrate, where the aggregate volume of the solder trench is large enough to capture a flow of excess under-fill during fabrication. One advantage of the disclosed integrated circuit package is that the solder trench is used in lieu of solder dam structures, thereby allowing a stencil to be lowered closer to the substrate surface during fabrication, which facilitates depositing solder paste during fabrication.

Abstract translation: 一个实施例提出了一种集成电路封装，其包括衬底，安装在衬底上的一个或多个器件，被配置为将衬底上的一个或多个器件固定的底部填充层以及形成在衬底中的焊料沟槽， 焊料沟槽的总体积足够大以在制造期间捕获过量欠填充的流动。 所公开的集成电路封装的一个优点是使用焊接沟槽来代替焊料坝结构，从而允许在制造期间将模板降低到靠近衬底表面，这有助于在制造期间沉积焊膏。

公开(公告)号：US20150077918A1

公开(公告)日：2015-03-19

申请号：US14031714

申请日：2013-09-19

Applicant: Nvidia Corporation

Inventor： Leilei Zhang ,  Ron Boja ,  Abraham Yee ,  Zuhair Bokharey

IPC: H05K1/14 ,  G06F1/18 ,  H05K3/30 ,  H05K1/02

CPC classification number: G06F1/183 ,  H01L23/16 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48229 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15331 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K2201/2009 ,  Y10T29/4913 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/0401

Abstract: Stiffening is provided for an electronic package assembly having a substrate. A first electronic package, having a first function, is electromechanically fastened to a first surface of the substrate with a first array of electrically conductive interconnects, which is disposed over a central area of the substrate first surface. A second electronic package, having a second function, is fastened to the first substrate surface with a second conductive interconnect array. At least a pair of the first array conductors is electrically coupled to at least a pair of the second array conductors for data/signal exchange and at least a component of the first electronic package interacts with at least a component of the second package. A metallic stiffener ring is disposed about an outer periphery of at least the central area of the substrate.

Abstract translation: 为具有基板的电子封装组件提供加强。 具有第一功能的第一电子封装通过设置在衬底第一表面的中心区域上的第一导电互连阵列机电地紧固到衬底的第一表面。 具有第二功能的第二电子封装件用第二导电互连阵列紧固到第一衬底表面。 至少一对第一阵列导体电耦合到至少一对第二阵列导体用于数据/信号交换，并且第一电子封装的至少一个部件与第二封装的至少一个部件相互作用。 金属加强环围绕至少基板的中心区域的外周设置。

公开(公告)号：US09760132B2

公开(公告)日：2017-09-12

申请号：US14031714

申请日：2013-09-19

Applicant: Nvidia Corporation

Inventor： Leilei Zhang ,  Ron Boja ,  Abraham Yee ,  Zuhair Bokharey

IPC: H01L23/16 ,  G06F1/18 ,  H01L25/10 ,  H01L25/00 ,  H05K1/02 ,  H01L23/498 ,  H01L23/00

CPC classification number: G06F1/183 ,  H01L23/16 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L24/73 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2224/26175 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48229 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15331 ,  H01L2924/3511 ,  H05K1/0271 ,  H05K2201/2009 ,  Y10T29/4913 ,  H01L2224/48227 ,  H01L2924/00012 ,  H01L2224/16225 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/0401

Abstract: Stiffening is provided for an electronic package assembly having a substrate. A first electronic package, having a first function, is electromechanically fastened to a first surface of the substrate with a first array of electrically conductive interconnects, which is disposed over a central area of the substrate first surface. A second electronic package, having a second function, is fastened to the first substrate surface with a second conductive interconnect array. At least a pair of the first array conductors is electrically coupled to at least a pair of the second array conductors for data/signal exchange and at least a component of the first electronic package interacts with at least a component of the second package. A metallic stiffener ring is disposed about an outer periphery of at least the central area of the substrate.

公开(公告)号：US20140124913A1

公开(公告)日：2014-05-08

申请号：US13668077

申请日：2012-11-02

Applicant: NVIDIA CORPORATION

Inventor： Leilei Zhang ,  Ron Boja ,  Abraham Yee ,  Zuhair Bokharey

IPC: H01L23/52

CPC classification number: H01L23/3128 ,  H01L23/42 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/16 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2924/3512 ,  H05K1/0271 ,  H05K3/4644 ,  H05K2201/09136 ,  H05K2201/2009 ,  H01L2224/05599

Abstract: A packaging substrate, a packaged semiconductor device, a computing device and methods for forming the same are provided. In one embodiment, a packaging substrate is provided that includes a packaging structure having a chip mounting surface and a bottom surface. The packaging structure has at a plurality of conductive paths formed between the chip mounting surface and the bottom surface. The conductive paths are configured to provide electrical connection between an integrated circuit chip disposed on the chip mounting surface and the bottom surface of the packaging structure. The packaging structure has an opening formed in the chip mounting surface proximate a perimeter of the packaging structure. A stiffening microstructure is disposed in the opening and is coupled to the packaging structure.

Abstract translation: 提供了一种封装基板，封装半导体器件，计算装置及其形成方法。 在一个实施例中，提供了包括具有芯片安装表面和底面的封装结构的封装基板。 封装结构具有形成在芯片安装表面和底表面之间的多个导电路径。 导电路径被配置为在布置在芯片安装表面上的集成电路芯片和封装结构的底表面之间提供电连接。 包装结构具有接近包装结构的周边的芯片安装表面中形成的开口。 加强的微观结构设置在开口中并且联接到包装结构。

公开(公告)号：US20140124254A1

公开(公告)日：2014-05-08

申请号：US13669289

申请日：2012-11-05

Applicant: NVIDIA CORPORATION

Inventor： Leilei ZHANG ,  Ron Boja ,  Abraham F. YEE ,  Zuhair BOKHAREY

IPC: H05K1/18 ,  H05K3/30

CPC classification number: H01L23/49894 ,  H01L23/50 ,  H01L24/13 ,  H01L24/16 ,  H01L25/16 ,  H01L2224/131 ,  H01L2224/16237 ,  H01L2924/15311 ,  H05K3/28 ,  H05K3/3452 ,  H05K2201/0376 ,  H05K2201/09881 ,  H05K2201/0989 ,  Y10T29/49124 ,  H01L2924/014

Abstract: Embodiments of the present invention provide a packaging system, which generally includes a substrate, a first electrical conductive pad and a second electrical conductive pad formed on a top surface of the substrate, and a mask section formed on the top surface of the substrate and disposed between the first electrical conductive pad and the second electrical conductive pad. The packaging system further includes a passive component mounted onto a top surface of the mask section, wherein a portion of a back surface of the passive component is in physical contact with the first electrical conductive pad and the second electrical conductive pad, respectively.

Abstract translation: 本发明的实施例提供了一种包装系统，其通常包括基板，形成在基板的顶表面上的第一导电焊盘和第二导电焊盘，以及形成在基板的顶表面上的掩模部， 在第一导电焊盘和第二导电焊盘之间。 包装系统还包括安装在掩模部分的顶表面上的无源部件，其中无源部件的后表面的一部分分别与第一导电焊盘和第二导电焊盘物理接触。