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公开(公告)号：US11409597B2
公开(公告)日：2022-08-09
申请号：US16811499
申请日：2020-03-06
Applicant: NVIDIA Corp.
Inventor： Michael Sullivan , Siva Hari , Brian Zimmer , Timothy Tsai , Stephen W. Keckler
Abstract: An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.
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公开(公告)号：US20200210276A1
公开(公告)日：2020-07-02
申请号：US16811499
申请日：2020-03-06
Applicant: NVIDIA Corp.
Inventor： Michael Sullivan , Siva Hari , Brian Zimmer , Timothy Tsai , Stephen W. Keckler
Abstract: An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.
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公开(公告)号：US20190102242A1
公开(公告)日：2019-04-04
申请号：US15845314
申请日：2017-12-18
Applicant: NVIDIA Corp.
Inventor： Michael Sullivan , Siva Hari , Brian Zimmer , Timothy Tsai , Stephen W. Keckler
Abstract: A family of software-hardware cooperative mechanisms to accelerate intra-thread duplication leverage the register file error detection hardware to implicitly check the data from duplicate instructions, avoiding the overheads of instruction checking and enforcing low-latency error detection with strict error containment guarantees.
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