公开(公告)号：US12131800B2

公开(公告)日：2024-10-29

申请号：US18056158

申请日：2022-11-16

Applicant: NVIDIA Corp.

Inventor： Mahmut Ersin Sinangil ,  Sudhir Shrikantha Kudva ,  Nikola Nedovic ,  Carl Thomas Gray

IPC: G11C7/24 ,  G11C7/10 ,  G11C7/20

CPC classification number: G11C7/24 ,  G11C7/1063 ,  G11C7/20

Abstract: PUF cells utilizing a dual-interlocking scheme demonstrating improved noise immunity and stability across different V/T conditions and different uses over time in noisy environments. The PUF cell may be advantageously utilized in conjunction with error detection techniques that screen out unstable cells. A set of such PUF cells utilized to generate a device-specific bit pattern, for example a master key.

公开(公告)号：US20250105734A1

公开(公告)日：2025-03-27

申请号：US18895180

申请日：2024-09-24

Applicant: NVIDIA Corp.

Inventor： Siddharth Saxena ,  Sudhir Shrikantha Kudva ,  Miguel Rodriguez ,  Vijay Srinivasan ,  Tezaswi Raja ,  Carl Thomas Gray ,  Santosh Santosh

IPC: H02M3/155 ,  H01L23/528

Abstract: Power delivery systems for integrated circuits that include a first metal path traversing first metal layers from a global power domain supply to a voltage regulator, a second metal path traversing second metal layers from a local power domain supply to the voltage regulator, and a third metal path traversing third metal layers from the local power domain supply to an integrated circuit. Electrical isolation gaps are formed between the first metal layers, the second metal layers, and the third metal layers.

公开(公告)号：US11784835B2

公开(公告)日：2023-10-10

申请号：US17481154

申请日：2021-09-21

Applicant: NVIDIA Corp.

Inventor： Sudhir Shrikantha Kudva ,  Nikola Nedovic ,  Carl Thomas Gray ,  Stephen G Tell

IPC: H04L9/32 ,  H04L9/08

CPC classification number: H04L9/3278 ,  H04L9/0825 ,  H04L9/0861 ,  H04L2209/12

Abstract: A circuit includes a set of multiple bit generating cells. One or more adjustable characterization circuits are coupled to inputs to the bit generating cells to affect the outputs of the bit generating cells. Based on the effect of the characterization circuit(s) on the outputs of the bit generating cells, a subset less than all of the bit generating cells is selected.

公开(公告)号：US20220271952A1

公开(公告)日：2022-08-25

申请号：US17481154

申请日：2021-09-21

Applicant: NVIDIA Corp.

Inventor： Sudhir Shrikantha Kudva ,  Nikola Nedovic ,  Carl Thomas Gray ,  Stephen G Tell

IPC: H04L9/32 ,  H04L9/08

Abstract: A circuit includes a set of multiple bit generating cells. One or more adjustable characterization circuits are coupled to inputs to the bit generating cells to affect the outputs of the bit generating cells. Based on the effect of the characterization circuit(s) on the outputs of the bit generating cells, a subset less than all of the bit generating cells is selected.

公开(公告)号：US10999051B2

公开(公告)日：2021-05-04

申请号：US16905635

申请日：2020-06-18

Applicant: NVIDIA Corp.

Inventor： Xi Chen ,  Nikola Nedovic ,  Carl Thomas Gray ,  Stephen G Tell

IPC: H04L7/00 ,  H04B1/12 ,  H04B1/16 ,  H03K3/037

Abstract: A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction based on a clock duty cycle error is applied to data receiver front ends.

公开(公告)号：US10566958B1

公开(公告)日：2020-02-18

申请号：US16248558

申请日：2019-01-15

Applicant: NVIDIA Corp.

Inventor： Sanquan Song ,  Olakanmi Oluwole ,  John Poulton ,  Carl Thomas Gray

IPC: H03L7/099 ,  H03B27/00 ,  H03B1/04 ,  H03K3/012 ,  G06F1/06 ,  G06F1/10 ,  H03K3/03

Abstract: Injection locked oscillation circuits are applied along clock distribution circuit paths to increase clock signal bandwidth, reduce duty cycle error, reduce quadrature phase error, reduce clock signal jitter, and reduce clock signal power consumption.

公开(公告)号：US11411563B1

公开(公告)日：2022-08-09

申请号：US17184396

申请日：2021-02-24

Applicant: NVIDIA Corp.

Inventor： Sudhir Shrikantha Kudva ,  Nikola Nedovic ,  Carl Thomas Gray

IPC: H03K19/17768 ,  H04L9/32 ,  H04L9/08 ,  H03K19/173 ,  H03K19/17748 ,  H03K19/17704 ,  H03K19/17756 ,  H03K19/177

Abstract: A circuit includes a set of multiple bit generating cells. One or more adjustable current sources is coupled to introduce perturbations into outputs of the bit generating cells. Based on the perturbations, the outputs of a subset less than all of the bit generating cells are selected, and applied as a control.

公开(公告)号：US20210083837A1

公开(公告)日：2021-03-18

申请号：US16927017

申请日：2020-07-13

Applicant: NVIDIA Corp.

Inventor： Xi Chen ,  Nikola Nedovic ,  Carl Thomas Gray ,  Stephen G Tell

IPC: H04L7/00

Abstract: A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction is computed as a global offset value based on a clock duty cycle error, combined with a local offset value for each data lane, and is applied to data receiver front ends.

公开(公告)号：US20210083836A1

公开(公告)日：2021-03-18

申请号：US16905635

申请日：2020-06-18

Applicant: NVIDIA Corp.

Inventor： Xi Chen ,  Nikola Nedovic ,  Carl Thomas Gray ,  Stephen G. Tell

IPC: H04L7/00 ,  H03K3/037 ,  H04B1/12 ,  H04B1/16

Abstract: A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction based on a clock duty cycle error is applied to data receiver front ends.

公开(公告)号：US20240161800A1

公开(公告)日：2024-05-16

申请号：US18056158

申请日：2022-11-16

Applicant: NVIDIA Corp.

Inventor： Mahmut Ersin Sinangil ,  Sudhir Shrikantha Kudva ,  Nikola Nedovic ,  Carl Thomas Gray

IPC: G11C7/24 ,  G11C7/10 ,  G11C7/20

CPC classification number: G11C7/24 ,  G11C7/1063 ,  G11C7/20

Abstract: PUF cells utilizing a dual-interlocking scheme demonstrating improved noise immunity and stability across different V/T conditions and different uses over time in noisy environments. The PUF cell may be advantageously utilized in conjunction with error detection techniques that screen out unstable cells. A set of such PUF cells utilized to generate a device-specific bit pattern, for example a master key.