公开(公告)号：US20240411977A1

公开(公告)日：2024-12-12

申请号：US18330057

申请日：2023-06-06

Applicant: NVIDIA Corp.

Inventor： Chia-Tung HO ,  Haoxing Ren

IPC: G06F30/394 ,  G06F30/392

Abstract: Lattice graph routability modelling mechanisms for standard cells utilizing a trained lattice graph routability model to determine routability metrics for local areas and global net connections in the standard cell. The metrics are applied to influence transistor placement in the standard cell, resulting in standard cell layouts with improved routability. Circuit layout generating processes are also described, in which a layout is formed lacking external pin assignments, and during routing of the nets for the circuit, a graph comprising virtual nodes and edges from the virtual nodes to grid locations for pins external to the circuit is generated. Routing to the external net of the circuit is performed according to the graph nodes and the graph edges.

公开(公告)号：US20240411974A1

公开(公告)日：2024-12-12

申请号：US18330139

申请日：2023-06-06

Applicant: NVIDIA Corp.

Inventor： Chia-Tung HO ,  Haoxing Ren

IPC: G06F30/392 ,  G06F30/394

Abstract: Lattice graph routability modelling mechanisms for standard cells utilizing a trained lattice graph routability model to determine routability metrics for local areas and global net connections in the standard cell. The metrics are applied to influence transistor placement in the standard cell, resulting in standard cell layouts with improved routability. Circuit layout generating processes are also described, in which a layout is formed lacking external pin assignments, and during routing of the nets for the circuit, a graph comprising virtual nodes and edges from the virtual nodes to grid locations for pins external to the circuit is generated. Routing to the external net of the circuit is performed according to the graph nodes and the graph edges.

公开(公告)号：US11651194B2

公开(公告)日：2023-05-16

申请号：US16859585

申请日：2020-04-27

Applicant: NVIDIA Corp.

Inventor： Haoxing Ren ,  George Kokai ,  Ting Ku ,  Walker Joseph Turner

IPC: G06F16/901 ,  G06F17/16 ,  G06N3/045

CPC classification number: G06N3/045 ,  G06F16/9024 ,  G06F17/16

Abstract: A graph neural network to predict net parasitics and device parameters by transforming circuit schematics into heterogeneous graphs and performing predictions on the graphs. The system may achieve an improved prediction rate and reduce simulation errors.

公开(公告)号：US11645533B2

公开(公告)日：2023-05-09

申请号：US15929242

申请日：2020-03-17

Applicant: NVIDIA Corp.

Inventor： Zhiyao Xie ,  Haoxing Ren ,  Brucek Khailany ,  Sheng Ye

IPC: G06N3/084 ,  G06F30/398 ,  G06N3/04 ,  G06F119/06

CPC classification number: G06N3/084 ,  G06F30/398 ,  G06N3/04 ,  G06F2119/06

Abstract: IR drop predictions are obtained using a maximum convolutional neural network. A circuit structure is partitioned into a grid. For cells of the circuit structure in sub-intervals of a clock period, power consumption of the cell is amortized into a set of grid tiles that include portions of the cell, thus forming a set of power maps. The power maps are applied to a neural network to generate IR drop predictions for the circuit structure.

公开(公告)号：US20210158155A1

公开(公告)日：2021-05-27

申请号：US16992354

申请日：2020-08-13

Applicant: NVIDIA Corp.

Inventor： Yanqing Zhang ,  Haoxing Ren ,  Brucek Khailany

IPC: G06N3/08 ,  G06N3/04 ,  G06N5/04 ,  G06K9/62 ,  G06F11/30 ,  G06F11/34

Abstract: A graph neural network for average power estimation of netlists is trained with register toggle rates over a power window from an RTL simulation and gate level netlists as input features. Combinational gate toggle rates are applied as labels. The trained graph neural network is then applied to infer combinational gate toggle rates over a different power window of interest and/or different netlist.

公开(公告)号：US20200327417A1

公开(公告)日：2020-10-15

申请号：US15929242

申请日：2020-03-17

Applicant: NVIDIA Corp.

Inventor： Zhiyao Xie ,  Haoxing Ren ,  Brucek Khailany ,  Sheng Ye

IPC: G06N3/08 ,  G06N3/04 ,  G06F30/398

Abstract: IR drop predictions are obtained using a maximum convolutional neural network. A circuit structure is partitioned into a grid. For cells of the circuit structure in sub-intervals of a clock period, power consumption of the cell is amortized into a set of grid tiles that include portions of the cell, thus forming a set of power maps. The power maps are applied to a neural network to generate IR drop predictions for the circuit structure.

公开(公告)号：US12169677B2

公开(公告)日：2024-12-17

申请号：US17230592

申请日：2021-04-14

Applicant: NVIDIA Corp.

Inventor： Haoxing Ren ,  Matthew Rudolph Fojtik

IPC: G06F30/398 ,  G06F30/394 ,  G06N3/047 ,  G06N3/12

Abstract: A genetic algorithm is utilized to generate routing candidates to which a reinforcement learning model is applied to correct the design rule constraint violations incrementally. A design rule checker provides feedback on the violations to the reinforcement learning model and the model learns how to fix the violations. A layout device placer based upon a simulated annealing method may also be utilized.

公开(公告)号：US20220292335A1

公开(公告)日：2022-09-15

申请号：US17679681

申请日：2022-02-24

Applicant: NVIDIA Corp.

Inventor： Haoxing Ren

IPC: G06N3/063 ,  G06N3/08 ,  G06N3/04

Abstract: An automatic standard cell layout generator that generates circuit layouts for an industry standard cell library on an advanced technology node leverages reinforcement learning (RL) to generate device placements in the layouts and also to fix design rule violations during routing. A genetic algorithm is utilized to generate routing candidates to which a reinforcement learning model is applied to correct the design rule constraint violations incrementally. A design rule checker provides feedback on the violations to the reinforcement learning model and the model learns how to fix the violations. A layout device placer based upon a simulated annealing method may also be utilized.

公开(公告)号：US20230237313A1

公开(公告)日：2023-07-27

申请号：US18295145

申请日：2023-04-03

Applicant: NVIDIA Corp.

Inventor： Haoxing Ren ,  George Ferenc Kokai ,  Ting Ku ,  Walker Joseph Turner

IPC: G06N3/045 ,  G06F16/901 ,  G06F17/16

CPC classification number: G06N3/045 ,  G06F16/9024 ,  G06F17/16

Abstract: A graph neural network to predict net parasitics and device parameters by transforming circuit schematics into heterogeneous graphs and performing predictions on the graphs. The system may achieve an improved prediction rate and reduce simulation errors.

公开(公告)号：US20210158127A1

公开(公告)日：2021-05-27

申请号：US16859585

申请日：2020-04-27

Applicant: NVIDIA Corp.

Inventor： Haoxing Ren ,  George Kokai ,  Ting Ku ,  Walker Joseph Turner

IPC: G06N3/04 ,  G06F17/16 ,  G06F16/901

Abstract: A graph neural network to predict net parasitics and device parameters by transforming circuit schematics into heterogeneous graphs and performing predictions on the graphs. The system may achieve an improved prediction rate and reduce simulation errors.