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公开(公告)号：US11824533B1
公开(公告)日：2023-11-21
申请号：US17814752
申请日：2022-07-25
Applicant: NVIDIA Corp.
Inventor： Walker Joseph Turner , John Poulton , Sanquan Song
IPC: H03K19/0185 , H03K3/037
CPC classification number: H03K19/018528 , H03K3/037 , H03K19/018521
Abstract: Voltage level conversion circuits include PMOS pull-down devices or NMOS pull-up devices, and inverters with outputs that determine gate voltages of these devices. The inverters are powered by moving supply voltages, for example complementary supply voltages generated from a pair of cross-coupled inverters. The cross-coupled inverters may implement a data storage latch with the moving supply voltages generated from the internal data storage nodes of the latch.
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公开(公告)号：US12009816B2
公开(公告)日：2024-06-11
申请号：US17932052
申请日：2022-09-14
Applicant: NVIDIA Corp.
Inventor： Walker Joseph Turner , John Poulton , Sanquan Song
IPC: H03K19/0185 , H03K3/037 , H03K19/00 , H03K3/356
CPC classification number: H03K19/018521 , H03K3/037 , H03K19/0013 , H03K19/018528 , H03K3/356165
Abstract: A level-shifting circuits utilizing storage cells for shifting signals low-to-high or high-to-low include control drivers with moving supply voltages. The moving supply voltages may power positive or negative supply terminals of the control drivers. The control drivers drive gates of common-source configured devices coupled to storage nodes of the storage cell.
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公开(公告)号：US20240030917A1
公开(公告)日：2024-01-25
申请号：US17932075
申请日：2022-09-14
Applicant: NVIDIA Corp.
Inventor： Walker Joseph Turner , John Poulton , Sanquan Song
IPC: H03K19/0185 , H03K19/00
CPC classification number: H03K19/018521 , H03K19/0013 , H03K3/356165
Abstract: Stacked voltage domain level shifting circuits for shifting signals low-to-high or high-to-low include a storage cell and control drivers powered by a mid-range supply rail of the stacked voltage domain level shifting circuit, wherein the control drivers are coupled to drive common-source configured devices coupled to storage nodes of the storage cell.
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公开(公告)号：US11632275B2
公开(公告)日：2023-04-18
申请号：US17243035
申请日：2021-04-28
Applicant: NVIDIA Corp.
Inventor： Sanquan Song , John Poulton
Abstract: A transceiver circuit includes a receiver front end utilizing a ring oscillator, and a transmitter front end utilizing a pass-gate circuit in a first feedback path across a last-stage driver circuit. The transceiver circuit provides low impedance at low frequency and high impedance at high frequency, and desirable peaking behavior.
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公开(公告)号：US10601324B1
公开(公告)日：2020-03-24
申请号：US16387383
申请日：2019-04-17
Applicant: NVIDIA Corp.
Inventor： Sudhir Shrikantha Kudva , Ahmed Abou-Alfotouh , Nikola Nedovic , John Poulton
Abstract: A DC-DC converter circuit includes a switched tank converter configured to output a switching waveform. The DC-DC converter circuit further includes a transformer coupled to the switched tank converter to receive the switching waveform output by the switched tank converter across a primary winding of the transformer.
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Patent Agency Ranking
公开(公告)号：US12255675B2
公开(公告)日：2025-03-18
申请号：US17931472
申请日：2022-09-12
Applicant: NVIDIA Corp.
Inventor： Xi Chen , Yoshinori Nishi , John Poulton
Abstract: A simultaneous bi-directional (SBD) transceiver includes a main transmit driver, a replica transmit driver, and a series-series-bridged (SSB) tri-impedance network. A pre-driver stage includes parallel delay paths for the main transmit driver and the replica transmit driver, enabling the delay for signals received by the main transmit driver and the replica transmit driver to be independently configured.
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公开(公告)号：US11936507B2
公开(公告)日：2024-03-19
申请号：US18182245
申请日：2023-03-10
Applicant: NVIDIA Corp.
Inventor： Sanquan Song , John Poulton
CPC classification number: H04L25/4917 , H04B1/0082
Abstract: A transceiver circuit includes a receiver front end utilizing a ring oscillator, and a transmitter front end utilizing a pass-gate circuit in a first feedback path across a last-stage driver circuit. The transceiver circuit provides low impedance at low frequency and high impedance at high frequency, and desirable peaking behavior.
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公开(公告)号：US20240030918A1
公开(公告)日：2024-01-25
申请号：US17932091
申请日：2022-09-14
Applicant: NVIDIA Corp.
Inventor： Walker Joseph Turner , John Poulton , Sanquan Song
IPC: H03K19/0185 , H03K19/00
CPC classification number: H03K19/018521 , H03K19/0013 , H03K3/356165
Abstract: Stacked voltage domain level shifting circuits for shifting signals low-to-high or high-to-low include a storage cell powered by a mid-range supply rail of the stacked voltage domain level shifting circuit, and control drivers powered by moving supply voltages generated by the storage cell, wherein the control drivers coupled to drive gates of common-source configured devices coupled to storage nodes of the storage cell.
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9.发明公开公开(公告)号：US20230246661A1
公开(公告)日：2023-08-03
申请号：US17931472
申请日：2022-09-12
Applicant: NVIDIA Corp.
Inventor： Xi Chen , Yoshinori Nishi , John Poulton
CPC classification number: H04B1/0483 , H03H7/38 , H04B1/38
Abstract: A simultaneous bi-directional (SBD) transceiver includes a main transmit driver, a replica transmit driver, and a series-series-bridged (SSB) tri-impedance network. A pre-driver stage includes parallel delay paths for the main transmit driver and the replica transmit driver, enabling the delay for signals received by the main transmit driver and the replica transmit driver to be independently configured.
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公开(公告)号：US12047067B2
公开(公告)日：2024-07-23
申请号：US17932091
申请日：2022-09-14
Applicant: NVIDIA Corp.
Inventor： Walker Joseph Turner , John Poulton , Sanquan Song
IPC: H03K19/0185 , H03K3/037 , H03K19/00 , H03K3/356
CPC classification number: H03K19/018521 , H03K3/037 , H03K19/0013 , H03K19/018528 , H03K3/356165
Abstract: Stacked voltage domain level shifting circuits for shifting signals low-to-high or high-to-low include a storage cell powered by a mid-range supply rail of the stacked voltage domain level shifting circuit, and control drivers powered by moving supply voltages generated by the storage cell, wherein the control drivers coupled to drive gates of common-source configured devices coupled to storage nodes of the storage cell.
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