公开(公告)号：US20190305765A1

公开(公告)日：2019-10-03

申请号：US16295886

申请日：2019-03-07

Applicant: NVIDIA Corp.

Inventor： Donghyuk Lee ,  James Michael O'Connor ,  John Wilson

IPC: H03K7/02 ,  H04B14/02 ,  G06F13/42

Abstract: Mechanisms to reduce noise and/or energy consumption in PAM communication systems, utilizing conditional symbol substitution in each burst interval of a multi-data lane serial data bus.

公开(公告)号：US10404505B1

公开(公告)日：2019-09-03

申请号：US16172489

申请日：2018-10-26

Applicant: NVIDIA Corp.

Inventor： John Wilson

IPC: H04L27/04 ,  H03K19/177 ,  H04N19/184

Abstract: A system comprising a PAM-4 transmitter coupled data lanes includes a least significant bit section and a most significant bit section for the symbols generated on each lane. A controller to determine a state of the PAM-4 transmitter and selectively inverts a polarity of the symbol bits on the lanes based on the state.

公开(公告)号：US20190250657A1

公开(公告)日：2019-08-15

申请号：US16135977

申请日：2018-09-19

Applicant: NVIDIA Corp.

Inventor： Sudhir Kudva ,  John Wilson

IPC: G05F1/614 ,  G05F1/46

CPC classification number: G05F1/462 ,  G05F1/563 ,  G05F1/565 ,  G05F1/575

Abstract: High-resolution switched digital regulators are disclosed having fast cross corner and variable temperature response, with constrained ripple. The strength of the power transistors utilized by the regulator are adjusted to control the current delivered to the load. The regulators utilize a slow control loop in parallel with a primary fast switching loop. The slow loop uses the switching signal of the primary loop to estimate the load current and set the power transistor size accordingly.

公开(公告)号：US11144080B2

公开(公告)日：2021-10-12

申请号：US16723700

申请日：2019-12-20

Applicant: NVIDIA Corp.

Inventor： Sudhir Kudva ,  John Wilson

IPC: G05F1/42 ,  G05F1/46 ,  G05F1/563 ,  G05F1/565 ,  G05F1/575

Abstract: High-resolution switched digital regulators are disclosed having fast cross corner and variable temperature response, with constrained ripple. The strength of the power transistors utilized by the regulator are adjusted to control the current delivered to the load. The regulators utilize a slow control loop in parallel with a primary fast switching loop. The slow loop uses the switching signal of the primary loop to estimate the load current and set the power transistor size accordingly.

公开(公告)号：US10599606B2

公开(公告)日：2020-03-24

申请号：US16360212

申请日：2019-03-21

Applicant: NVIDIA Corp.

Inventor： Donghyuk Lee ,  James Michael O'Connor ,  John Wilson

IPC: G06F3/00 ,  G06F13/42 ,  H04L25/49 ,  G06F13/40

Abstract: Methods of operating a serial data bus generate two-level bridge symbols to insert between four-level symbols on one or more data lanes of the serial data bus, to reduce voltage deltas on the one or more data lanes during data transmission on the serial data bus.

公开(公告)号：US20200028708A1

公开(公告)日：2020-01-23

申请号：US16190467

申请日：2018-11-14

Applicant: NVIDIA Corp.

Inventor： John Wilson ,  Sunil Sudhakaran

IPC: H04L12/40 ,  G06F13/40

Abstract: An encoding process for bus data utilizes data from multiple data line groups on a multi-byte wide bus where each group has an associated DBI line. The process leverages the expanded encoding space for the multiple groups and associated multiple DBI bits. This process may be expanded to four bytes, eight bytes, etc.

公开(公告)号：US20190305995A1

公开(公告)日：2019-10-03

申请号：US16368472

申请日：2019-03-28

Applicant: NVIDIA Corp.

Inventor： Donghyuk Lee ,  James Michael O'Connor ,  John Wilson

IPC: H04L25/49 ,  H04B3/32 ,  H04L1/00

Abstract: Methods of operating a serial data bus divide series of data bits into sequences of one or more bits and encode the sequences as N-level symbols, which are then transmitted at multiple discrete voltage levels. These methods may be utilized to communicate over serial data lines to improve bandwidth and reduce crosstalk and other sources of noise.

公开(公告)号：US20200264642A1

公开(公告)日：2020-08-20

申请号：US16723700

申请日：2019-12-20

Applicant: NVIDIA Corp.

Inventor： Sudhir Kudva ,  John Wilson

IPC: G05F1/46 ,  G05F1/575 ,  G05F1/565 ,  G05F1/563

Abstract: High-resolution switched digital regulators are disclosed having fast cross corner and variable temperature response, with constrained ripple. The strength of the power transistors utilized by the regulator are adjusted to control the current delivered to the load. The regulators utilize a slow control loop in parallel with a primary fast switching loop. The slow loop uses the switching signal of the primary loop to estimate the load current and set the power transistor size accordingly.

公开(公告)号：US10657094B2

公开(公告)日：2020-05-19

申请号：US16295595

申请日：2019-03-07

Applicant: NVIDIA Corp.

Inventor： Donghyuk Lee ,  James Michael O'Connor ,  John Wilson

IPC: G06F13/42 ,  H04L1/00 ,  H04L25/49

Abstract: Methods of operating a serial data bus divide series of data bits into sequences of one or more bits and encode the sequences as N-level symbols, which are then transmitted at multiple discrete voltage levels. These methods may be utilized to communicate over serial data lines to improve bandwidth and reduce crosstalk and other sources of noise.

公开(公告)号：US10558230B2

公开(公告)日：2020-02-11

申请号：US16135977

申请日：2018-09-19

Applicant: NVIDIA Corp.

Inventor： Sudhir Kudva ,  John Wilson

IPC: G05F1/46 ,  G05F1/563 ,  G05F1/565 ,  G05F1/575

Abstract: High-resolution switched digital regulators are disclosed having fast cross corner and variable temperature response, with constrained ripple. The strength of the power transistors utilized by the regulator are adjusted to control the current delivered to the load. The regulators utilize a slow control loop in parallel with a primary fast switching loop. The slow loop uses the switching signal of the primary loop to estimate the load current and set the power transistor size accordingly.