公开(公告)号：US20200174932A1

公开(公告)日：2020-06-04

申请号：US16222696

申请日：2018-12-17

Applicant: NVIDIA Corp.

Inventor： Jay Gupta ,  Gosagan Padmanabhan ,  Devesh Mittal ,  Kaushal Agarwal

IPC: G06F12/0808 ,  G06F12/1045

Abstract: A memory management unit responds to an invalidate by class command by identifying a marker for a class of cache entries that the invalidate by class command is meant to invalidate. The memory management unit stores the active marker as a retired marker and then sets the active marker to the next available marker. Thereafter, the memory management sends an acknowledgement signal (e.g., to the operating system) while invalidating the cache entries having the class and the retired marker in the background. By correlating markers with classes of cache entries, the memory management can more quickly respond to class invalidation requests.

公开(公告)号：US10754775B2

公开(公告)日：2020-08-25

申请号：US16222696

申请日：2018-12-17

Applicant: NVIDIA Corp.

Inventor： Jay Gupta ,  Gosagan Padmanabhan ,  Devesh Mittal ,  Kaushal Agarwal

IPC: G06F12/0808 ,  G06F12/1045

Abstract: A memory management unit responds to an invalidate by class command by identifying a marker for a class of cache entries that the invalidate by class command is meant to invalidate. The memory management unit stores the active marker as a retired marker and then sets the active marker to the next available marker. Thereafter, the memory management sends an acknowledgement signal (e.g., to the operating system) while invalidating the cache entries having the class and the retired marker in the background. By correlating markers with classes of cache entries, the memory management can more quickly respond to class invalidation requests.