公开(公告)号：US20210295169A1

公开(公告)日：2021-09-23

申请号：US17231866

申请日：2021-04-15

Applicant: NVIDIA Corp.

Inventor： Harbinder Sikka ,  Kaushik Narayanun ,  Lijuan Luo ,  Karthikeyan Natarajan ,  Manjunatha Gowda ,  Sandeep Gangundi

IPC: G06N3/08 ,  G06T1/20 ,  G06T11/20 ,  G06N3/04 ,  G06F30/323

Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.

公开(公告)号：US10663515B2

公开(公告)日：2020-05-26

申请号：US16175423

申请日：2018-10-30

Applicant: NVIDIA Corp.

Inventor： Kaushik Narayanun ,  Shantanu Sarangi

IPC: G01R31/28 ,  G01R31/3185 ,  G06F13/42 ,  G06T1/20 ,  G11C29/00

Abstract: A hardware controller of a device under test (DUT) communicates with a PCIe controller to fetch test data and control test execution. The hardware controller also communicates with a JTAG/IEEE 1500 component to set up the DUT into various test configurations and to trigger test execution. For SCAN tests, the hardware controller provides a high throughput direct access to the on-chip compressors/decompressors to load the scan data and to collect the test results.

公开(公告)号：US11574097B2

公开(公告)日：2023-02-07

申请号：US17231866

申请日：2021-04-15

Applicant: NVIDIA Corp.

Inventor： Harbinder Sikka ,  Kaushik Narayanun ,  Lijuan Luo ,  Karthikeyan Natarajan ,  Manjunatha Gowda ,  Sandeep Gangundi

IPC: G06F7/50 ,  G06F30/327 ,  G06N3/08 ,  G06N7/00 ,  G06K9/62 ,  G06N3/04

Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.

公开(公告)号：US11010516B2

公开(公告)日：2021-05-18

申请号：US16537376

申请日：2019-08-09

Applicant: NVIDIA Corp.

Inventor： Harbinder Sikka ,  Kaushik Narayanun ,  Lijuan Luo ,  Karthikeyan Natarajan ,  Manjunatha Gowda ,  Sandeep Gangundi

IPC: G06F17/50 ,  G06F30/327 ,  G06N3/08 ,  G06N7/00 ,  G06K9/62 ,  G06N3/04

Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.

公开(公告)号：US20200151289A1

公开(公告)日：2020-05-14

申请号：US16537376

申请日：2019-08-09

Applicant: NVIDIA Corp.

Inventor： Harbinder Sikka ,  Kaushik Narayanun ,  Lijuan Luo ,  Karthikeyan Natarajan ,  Manjunatha Gowda ,  Sandeep Gangundi

IPC: G06F17/50 ,  G06N3/08 ,  G06N3/04 ,  G06K9/62 ,  G06N7/00

Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.

公开(公告)号：US20190128964A1

公开(公告)日：2019-05-02

申请号：US16175423

申请日：2018-10-30

Applicant: NVIDIA Corp.

Inventor： Kaushik Narayanun ,  Shantanu Sarangi

IPC: G01R31/3185 ,  G06F13/42 ,  G06T1/20

Abstract: A hardware controller of a device under test (DUT) communicates with a PCIe controller to fetch test data and control test execution. The hardware controller also communicates with a JTAG/IEEE 1500 component to set up the DUT into various test configurations and to trigger test execution. For SCAN tests, the hardware controller provides a high throughput direct access to the on-chip compressors/decompressors to load the scan data and to collect the test results.