公开(公告)号：US12131775B2

公开(公告)日：2024-10-29

申请号：US17678799

申请日：2022-02-23

Applicant: NVIDIA Corp.

Inventor： Lalit Gupta ,  Stefan P Sywyk ,  Andreas Jon Gotterba ,  Jesse Wang

IPC: G11C11/412

CPC classification number: G11C11/4125

Abstract: A static random access memory (SRAM) or other bit-storing cell arrangement includes memory cells and a hierarchical bitline structure including local bitlines for subsets of the memory banks and a global bitline spanning the subsets. A keeper circuit for the global bitline is replaced by bias circuitry on output transistors of the memory cells.

公开(公告)号：US20220406371A1

公开(公告)日：2022-12-22

申请号：US17350973

申请日：2021-06-17

Applicant: NVIDIA Corp.

Inventor： Lalit Gupta ,  Andreas Jon Gotterba ,  Jesse Wang ,  Stefan P. Sywyk

IPC: G11C11/418

Abstract: A machine memory includes multiple memory cells. Word lines, each with at least one word line driver, are coupled to the memory cells along rows. The word line drivers of at least some adjacent pairs of the word lines are coupled together by a pull-down transistor, in a manner that reduces read disturb of the memory cells.

公开(公告)号：US20240420748A1

公开(公告)日：2024-12-19

申请号：US18336758

申请日：2023-06-16

Applicant: NVIDIA Corp.

Inventor： Cagri Erbagci ,  Burak Erbagci ,  Lalit Gupta ,  Jesse San-Jey Wang

IPC: G11C7/12 ,  G11C7/10

Abstract: Negative bit line voltage assist mechanisms for multi-bank machine memories utilizing multiple local IO drivers include a shared boost capacitor configured to generate a negative bit line voltage assist for write operations by local IO drivers, where the boost capacitor is configured to selectively couple to one of the local IO drivers during the write operation.

公开(公告)号：US20240161815A1

公开(公告)日：2024-05-16

申请号：US18055047

申请日：2022-11-14

Applicant: NVIDIA Corp.

Inventor： Lalit Gupta ,  Jason Golbus ,  Jesse San-Jey Wang

IPC: G11C11/4096 ,  G11C11/4076 ,  G11C11/4094

CPC classification number: G11C11/4096 ,  G11C11/4076 ,  G11C11/4094

Abstract: Multi-ported memories that include write peripheral logic configured to operate in a first voltage domain, read peripheral logic configured to operate in a second voltage domain, and at least one bit cell array, wherein the write peripheral logic and the read peripheral logic are disposed on opposite sides of the bit cell array and voltage domain crossings between the first voltage domain and the second voltage domain are localized in bit cells of the at least one bit cell array.

公开(公告)号：US11854660B2

公开(公告)日：2023-12-26

申请号：US17556046

申请日：2021-12-20

Applicant: NVIDIA Corp.

Inventor： Lalit Gupta ,  Andreas Jon Gotterba ,  Jesse Wang

IPC: G11C7/12 ,  G11C5/06 ,  G11C7/22

CPC classification number: G11C7/12 ,  G11C5/063 ,  G11C7/22

Abstract: To mitigate pulse shape degradation along a signal route, the signal is driven from two ends. One end of the route is loaded and the other is relatively unloaded. The loaded route and unloaded route may traverse two different metal layers on a printed circuit board. The two routes may thus be related such that the unloaded route has less RC distortion effects on the signal than does the loaded route.

公开(公告)号：US20240395293A1

公开(公告)日：2024-11-28

申请号：US18323997

申请日：2023-05-25

Applicant: NVIDIA Corp.

Inventor： Lalit Gupta ,  Jason Golbus ,  Jesse San-Jey Wang

IPC: G11C7/10 ,  G11C7/18

Abstract: Mechanisms to mitigate signal race conditions in circuits that utilize multiple voltage domains. The mechanisms are applicable in signal fanout scenarios where leakage becomes problematic to signal timing, such machine memory devices, e.g., volatile single port or multi-port memory devices such as SRAMs (volatile static random access memory) or other bit-storing cell arrangements that include memory cells and a hierarchical bitline structure including local bitlines for subsets of the memory banks and a global bitline spanning the subsets.

公开(公告)号：US11804262B2

公开(公告)日：2023-10-31

申请号：US17350973

申请日：2021-06-17

Applicant: NVIDIA Corp.

Inventor： Lalit Gupta ,  Andreas Jon Gotterba ,  Jesse Wang ,  Stefan P Sywyk

IPC: G11C8/08 ,  G11C11/418

CPC classification number: G11C11/418

Abstract: A machine memory includes multiple memory cells. Word lines, each with at least one word line driver, are coupled to the memory cells along rows. The word line drivers of at least some adjacent pairs of the word lines are coupled together by a pull-down transistor, in a manner that reduces read disturb of the memory cells.

公开(公告)号：US20230267992A1

公开(公告)日：2023-08-24

申请号：US17678799

申请日：2022-02-23

Applicant: NVIDIA Corp.

Inventor： Lalit Gupta ,  Stefan P. Sywyk ,  Andreas Jon Gotterba ,  Jesse Wang

IPC: G11C11/412

CPC classification number: G11C11/4125

Abstract: A static random access memory (SRAM) or other bit-storing cell arrangement includes memory cells and a hierarchical bitline structure including local bitlines for subsets of the memory banks and a global bitline spanning the subsets. A keeper circuit for the global bitline is replaced by bias circuitry on output transistors of the memory cells.

公开(公告)号：US20230197127A1

公开(公告)日：2023-06-22

申请号：US17556046

申请日：2021-12-20

Applicant: NVIDIA Corp.

Inventor： Lalit Gupta ,  Andreas Jon Gotterba ,  Jesse Wang

IPC: G11C7/12 ,  G11C7/22 ,  G11C5/06

CPC classification number: G11C7/12 ,  G11C5/063 ,  G11C7/22

Abstract: To mitigate pulse shape degradation along a signal route, the signal is driven from two ends. One end of the route is loaded and the other is relatively unloaded. The loaded route and unloaded route may traverse two different metal layers on a printed circuit board. The two routes may thus be related such that the unloaded route has less RC distortion effects on the signal than does the loaded route.