公开(公告)号：US11470394B2

公开(公告)日：2022-10-11

申请号：US16934895

申请日：2020-07-21

Applicant: NVIDIA Corp.

Inventor： Hans Eberle ,  Larry Robert Dennison

IPC: H04N21/472 ,  H04N21/2387 ,  H04N21/6583 ,  H04L45/7453 ,  H04N21/43 ,  H04L47/283 ,  H04L45/00 ,  H04N21/234 ,  H04L47/62

Abstract: A communication method between a source device and a target device utilizes speculative connection setup between the source device and the target device, target-device-side packet ordering, and fine-grained ordering to remove packet dependencies.

公开(公告)号：US20200374594A1

公开(公告)日：2020-11-26

申请号：US16934895

申请日：2020-07-21

Applicant: NVIDIA Corp.

Inventor： Hans Eberle ,  Larry Robert Dennison

IPC: H04N21/472 ,  H04N21/2387 ,  H04N21/6583 ,  H04L12/743 ,  H04N21/43 ,  H04L12/841 ,  H04L12/733 ,  H04N21/234

Abstract: A communication method between a source device and a target device utilizes speculative connection setup between the source device and the target device, target-device-side packet ordering, and fine-grained ordering to remove packet dependencies.

公开(公告)号：US11799799B2

公开(公告)日：2023-10-24

申请号：US17377943

申请日：2021-07-16

Applicant: NVIDIA Corp.

Inventor： Matthias Augustin Blumrich ,  Nan Jiang ,  Larry Robert Dennison

IPC: H04L29/08 ,  H04L49/101 ,  H04L49/00 ,  H04L49/9047 ,  H04L49/253

CPC classification number: H04L49/101 ,  H04L49/254 ,  H04L49/3036 ,  H04L49/70 ,  H04L49/9047

Abstract: A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery.

公开(公告)号：US11363339B2

公开(公告)日：2022-06-14

申请号：US16933778

申请日：2020-07-20

Applicant: NVIDIA Corp.

Inventor： Hans Eberle ,  Larry Robert Dennison

IPC: H04N21/472 ,  H04N21/2387 ,  H04N21/6583 ,  H04L45/7453 ,  H04N21/43 ,  H04L47/283 ,  H04L45/00 ,  H04N21/234 ,  H04L47/62

Abstract: A communication method between a source device and a target device utilizes speculative connection setup between the source device and the target device, target-device-side packet ordering, and fine-grained ordering to remove packet dependencies.

公开(公告)号：US11108704B2

公开(公告)日：2021-08-31

申请号：US16703697

申请日：2019-12-04

Applicant: NVIDIA Corp.

Inventor： Matthias Augustin Blumrich ,  Nan Jiang ,  Larry Robert Dennison

IPC: H04L29/08 ,  H04L12/933 ,  H04L12/935 ,  H04L12/861 ,  H04L12/937 ,  H04L12/931

Abstract: A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery.

公开(公告)号：US20220095017A1

公开(公告)日：2022-03-24

申请号：US17539947

申请日：2021-12-01

Applicant: NVIDIA Corp.

Inventor： Hans Eberle ,  Larry Robert Dennison

IPC: H04N21/472 ,  H04N21/2387 ,  H04N21/6583 ,  H04L12/743 ,  H04N21/43 ,  H04L12/841 ,  H04L12/733 ,  H04N21/234

Abstract: A communication method between a source device and a target device utilizes speculative connection setup between the source device and the target device, target-device-side packet ordering, and fine-grained ordering to remove packet dependencies.

公开(公告)号：US10820057B2

公开(公告)日：2020-10-27

申请号：US16376988

申请日：2019-04-05

Applicant: NVIDIA Corp.

Inventor： Hans Eberle ,  Larry Robert Dennison

IPC: H04N21/472 ,  H04N21/2387 ,  H04N21/6583 ,  H04L12/743 ,  H04N21/43 ,  H04L12/841 ,  H04L12/733 ,  H04N21/234 ,  H04L12/863

Abstract: A communication method between a source device and a target device utilizes speculative connection setup between the source device and the target device, target-device-side packet ordering, and fine-grained ordering to remove packet dependencies.

公开(公告)号：US20200177521A1

公开(公告)日：2020-06-04

申请号：US16703697

申请日：2019-12-04

Applicant: NVIDIA Corp.

Inventor： Matthias Augustin Blumrich ,  Nan Jiang ,  Larry Robert Dennison

IPC: H04L12/933 ,  H04L12/935 ,  H04L12/931 ,  H04L12/937 ,  H04L12/861

Abstract: A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery.

公开(公告)号：US20250097153A1

公开(公告)日：2025-03-20

申请号：US18646410

申请日：2024-04-25

Applicant: NVIDIA Corp.

Inventor： John Martin Snyder ,  Nan Jiang ,  Dennis Charles Abts ,  Larry Robert Dennison

IPC: H04L47/122 ,  H04L47/125

Abstract: A process to manage congestion in a network involves converting traffic received from the local endpoints to a bandwidth demand for one or more destination endpoint in a remote group, and determining a sum over the destination endpoints of a minimum of a maximum bandwidth of a link and a bandwidth demand to one or more of the remote endpoints.

公开(公告)号：US11770215B2

公开(公告)日：2023-09-26

申请号：US17674167

申请日：2022-02-17

Applicant: NVIDIA Corp.

Inventor： Hans Eberle ,  Larry Robert Dennison ,  John Martin Snyder

IPC: H04L1/1607 ,  H04L1/1829

CPC classification number: H04L1/1628 ,  H04L1/1642 ,  H04L1/1835

Abstract: Packet flows between a transmitter and a receiver in an unreliable and unordered switched packet network may be established as a result of receiving a second packet comprising a second memory operation on a memory address. The transmission of memory load command packets followed by memory store command packets in the packet flow may be serialized, and a synchronization operation may be executed between the transmitter and the receiver when a packet count at the receiver satisfies a number of data packets in the packet flow.