公开(公告)号：US10957651B2

公开(公告)日：2021-03-23

申请号：US16534017

申请日：2019-08-07

Applicant: NVIDIA Corp.

Inventor： Don Templeton ,  Luke Young Chang ,  Narayan Kulshrestha

IPC: H01L23/538 ,  H01L23/50 ,  H01L25/065

Abstract: A die package is disclosed through which power domains within the chip may be isolated by removing vias within the package substrate, rather than power gating. Multiple substrate options may be configured without specific vias. This eliminates the need to design power gating circuitry into the die, freeing up that die area for more functional logic. The solution allows the die package to retain the same pinout for use by PCB designers, regardless of which power domains are gated.

公开(公告)号：US20210043574A1

公开(公告)日：2021-02-11

申请号：US16534017

申请日：2019-08-07

Applicant: NVIDIA Corp.

Inventor： Don Templeton ,  Luke Young Chang ,  Narayan Kulshrestha

IPC: H01L23/538 ,  H01L23/50 ,  H01L25/065

Abstract: A die package is disclosed through which power domains within the chip may be isolated by removing vias within the package substrate, rather than power gating. Multiple substrate options may be configured without specific vias. This eliminates the need to design power gating circuitry into the die, freeing up that die area for more functional logic. The solution allows the die package to retain the same pinout for use by PCB designers, regardless of which power domains are gated.