公开(公告)号：US20210295169A1

公开(公告)日：2021-09-23

申请号：US17231866

申请日：2021-04-15

Applicant: NVIDIA Corp.

Inventor： Harbinder Sikka ,  Kaushik Narayanun ,  Lijuan Luo ,  Karthikeyan Natarajan ,  Manjunatha Gowda ,  Sandeep Gangundi

IPC: G06N3/08 ,  G06T1/20 ,  G06T11/20 ,  G06N3/04 ,  G06F30/323

Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.

公开(公告)号：US11574097B2

公开(公告)日：2023-02-07

申请号：US17231866

申请日：2021-04-15

Applicant: NVIDIA Corp.

Inventor： Harbinder Sikka ,  Kaushik Narayanun ,  Lijuan Luo ,  Karthikeyan Natarajan ,  Manjunatha Gowda ,  Sandeep Gangundi

IPC: G06F7/50 ,  G06F30/327 ,  G06N3/08 ,  G06N7/00 ,  G06K9/62 ,  G06N3/04

Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.

公开(公告)号：US11010516B2

公开(公告)日：2021-05-18

申请号：US16537376

申请日：2019-08-09

Applicant: NVIDIA Corp.

Inventor： Harbinder Sikka ,  Kaushik Narayanun ,  Lijuan Luo ,  Karthikeyan Natarajan ,  Manjunatha Gowda ,  Sandeep Gangundi

IPC: G06F17/50 ,  G06F30/327 ,  G06N3/08 ,  G06N7/00 ,  G06K9/62 ,  G06N3/04

Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.

公开(公告)号：US20200151289A1

公开(公告)日：2020-05-14

申请号：US16537376

申请日：2019-08-09

Applicant: NVIDIA Corp.

Inventor： Harbinder Sikka ,  Kaushik Narayanun ,  Lijuan Luo ,  Karthikeyan Natarajan ,  Manjunatha Gowda ,  Sandeep Gangundi

IPC: G06F17/50 ,  G06N3/08 ,  G06N3/04 ,  G06K9/62 ,  G06N7/00

Abstract: Techniques to improve the accuracy and speed for detection and remediation of difficult to test nodes in a circuit design netlist. The techniques utilize improved netlist representations, test point insertion, and trained neural networks.