公开(公告)号：US20200177521A1

公开(公告)日：2020-06-04

申请号：US16703697

申请日：2019-12-04

Applicant: NVIDIA Corp.

Inventor： Matthias Augustin Blumrich ,  Nan Jiang ,  Larry Robert Dennison

IPC: H04L12/933 ,  H04L12/935 ,  H04L12/931 ,  H04L12/937 ,  H04L12/861

Abstract: A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery.

公开(公告)号：US20210344616A1

公开(公告)日：2021-11-04

申请号：US17377943

申请日：2021-07-16

Applicant: NVIDIA Corp.

Inventor： Matthias Augustin Blumrich ,  Nan Jiang ,  Larry Robert Dennison

IPC: H04L12/933 ,  H04L12/935 ,  H04L12/861 ,  H04L12/937 ,  H04L12/931

Abstract: A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery.

公开(公告)号：US11799799B2

公开(公告)日：2023-10-24

申请号：US17377943

申请日：2021-07-16

Applicant: NVIDIA Corp.

Inventor： Matthias Augustin Blumrich ,  Nan Jiang ,  Larry Robert Dennison

IPC: H04L29/08 ,  H04L49/101 ,  H04L49/00 ,  H04L49/9047 ,  H04L49/253

CPC classification number: H04L49/101 ,  H04L49/254 ,  H04L49/3036 ,  H04L49/70 ,  H04L49/9047

Abstract: A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery.

公开(公告)号：US11108704B2

公开(公告)日：2021-08-31

申请号：US16703697

申请日：2019-12-04

Applicant: NVIDIA Corp.

Inventor： Matthias Augustin Blumrich ,  Nan Jiang ,  Larry Robert Dennison

IPC: H04L29/08 ,  H04L12/933 ,  H04L12/935 ,  H04L12/861 ,  H04L12/937 ,  H04L12/931

Abstract: A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery.