公开(公告)号：US12099407B2

公开(公告)日：2024-09-24

申请号：US17737374

申请日：2022-05-05

Applicant: NVIDIA Corp.

Inventor： Michael Sullivan ,  Siva Kumar Sastry Hari ,  Brian Matthew Zimmer ,  Timothy Tsai ,  Stephen W. Keckler

IPC: G06F11/10 ,  G06F9/30 ,  G06F11/07

CPC classification number: G06F11/102 ,  G06F9/30029 ,  G06F9/30116 ,  G06F11/0772 ,  G06F11/1044

Abstract: An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.

公开(公告)号：US11409597B2

公开(公告)日：2022-08-09

申请号：US16811499

申请日：2020-03-06

Applicant: NVIDIA Corp.

Inventor： Michael Sullivan ,  Siva Hari ,  Brian Zimmer ,  Timothy Tsai ,  Stephen W. Keckler

IPC: G06F11/10 ,  G06F9/30 ,  G06F11/07

Abstract: An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.

公开(公告)号：US20200210276A1

公开(公告)日：2020-07-02

申请号：US16811499

申请日：2020-03-06

Applicant: NVIDIA Corp.

Inventor： Michael Sullivan ,  Siva Hari ,  Brian Zimmer ,  Timothy Tsai ,  Stephen W. Keckler

IPC: G06F11/10 ,  G06F11/07 ,  G06F9/30

Abstract: An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.

公开(公告)号：US20190102242A1

公开(公告)日：2019-04-04

申请号：US15845314

申请日：2017-12-18

Applicant: NVIDIA Corp.

Inventor： Michael Sullivan ,  Siva Hari ,  Brian Zimmer ,  Timothy Tsai ,  Stephen W. Keckler

IPC: G06F11/07 ,  G06F11/10 ,  G06F9/38 ,  G06F9/30

Abstract: A family of software-hardware cooperative mechanisms to accelerate intra-thread duplication leverage the register file error detection hardware to implicitly check the data from duplicate instructions, avoiding the overheads of instruction checking and enforcing low-latency error detection with strict error containment guarantees.

公开(公告)号：US20210004235A1

公开(公告)日：2021-01-07

申请号：US17024683

申请日：2020-09-17

Applicant: NVIDIA Corp.

Inventor： Siva Kumar Sastry Hari ,  Michael Sullivan ,  Timothy Tsai ,  Stephen W. Keckler

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/48 ,  G06F11/14 ,  G06F11/07

Abstract: A thread execution method in a processor includes executing original instructions of a first thread in a first execution lane of the processor, and interleaving execution of duplicated instructions of the first thread with execution of original instructions of a second thread in a second execution lane of the processor.

公开(公告)号：US20220269558A1

公开(公告)日：2022-08-25

申请号：US17737374

申请日：2022-05-05

Applicant: NVIDIA Corp.

Inventor： Michael Sullivan ,  Siva Kumar Sastry Hari ,  Brian Matthew Zimmer ,  Timothy Tsai ,  Stephen W. Keckler

IPC: G06F11/10 ,  G06F9/30 ,  G06F11/07

Abstract: An error reporting system utilizes a parity checker to receive data results from execution of an original instruction and a parity bit for the data. A decoder receives an error correcting code (ECC) for data resulting from execution of a shadow instruction of the original instruction, and data error correction is initiated on the original instruction result on condition of a mismatch between the parity bit and the original instruction result, and the decoder asserting a correctable error in the original instruction result.

公开(公告)号：US10817289B2

公开(公告)日：2020-10-27

申请号：US16150410

申请日：2018-10-03

Applicant: NVIDIA Corp.

Inventor： Siva Hari ,  Michael Sullivan ,  Timothy Tsai ,  Stephen W. Keckler ,  Abdulrahman Mahmoud

IPC: G06F11/14 ,  G06F9/30 ,  G06F11/10

Abstract: Software-only and software-hardware optimizations to reduce the overhead of intra-thread instruction duplication on a GPU or other instruction processor are disclosed. The optimizations trade off error containment for performance and include ISA extensions with limited hardware changes and area costs.

公开(公告)号：US20190102180A1

公开(公告)日：2019-04-04

申请号：US16150410

申请日：2018-10-03

Applicant: NVIDIA Corp.

Inventor： Siva Hari ,  Michael Sullivan ,  Timothy Tsai ,  Stephen W. Keckler ,  Abdulrahman Mahmoud

IPC: G06F9/30 ,  G06F11/10

CPC classification number: G06F9/30029 ,  G06F9/30032 ,  G06F9/30101 ,  G06F11/1044

Abstract: Software-only and software-hardware optimizations to reduce the overhead of intra -thread instruction duplication on a GPU or other instruction processor are disclosed. The optimizations trade off error containment for performance and include ISA extensions with limited hardware changes and area costs.