公开(公告)号：US11798923B2

公开(公告)日：2023-10-24

申请号：US17553519

申请日：2021-12-16

Applicant: NVIDIA Corp.

Inventor： Shuo Zhang ,  Eric Zhu ,  Minto Zheng ,  Michael Zhai ,  Town Zhang ,  Jie Ma

IPC: H01L23/538 ,  H01L25/10 ,  H01L25/16 ,  H05K1/18

CPC classification number: H01L25/105 ,  H01L23/5386 ,  H01L25/16 ,  H05K1/181 ,  H01L2225/107 ,  H01L2225/1094 ,  H05K2201/10015 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/10704

Abstract: Layout techniques for chip packages on printed circuit boards are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between chip packages while simultaneously providing for the rapid provision of transient power demands to the chip packages. The layout techniques may also enable improved thermal management for the chip packages.

公开(公告)号：US11616019B2

公开(公告)日：2023-03-28

申请号：US17128597

申请日：2020-12-21

Applicant: NVIDIA Corp.

Inventor： Jacky Qiu ,  Martin Ding ,  Jerry Zhou ,  Minto Zheng

IPC: H01L23/13 ,  H01L23/14 ,  H01L23/42 ,  H01L23/60 ,  H01L23/66 ,  H01L23/367 ,  H01L25/16 ,  H01L25/18 ,  H01L23/528 ,  H05K1/02 ,  H05K7/20 ,  H05K1/11 ,  H01L23/522

Abstract: A semiconductor assembly is described that includes a substrate having top and bottom sides. An integrated circuit die coupled to the substrate includes first and second distinct sets of ground pads. In some embodiments, the first and second sets of ground pads are configured to have distinct ground return paths to a host system. In further embodiments, one of the ground return paths may include a metal plate coupled between ground contacts on the top side of the substrate and ground contacts on a printed circuit board of the host system.

公开(公告)号：US20230411365A1

公开(公告)日：2023-12-21

申请号：US18462259

申请日：2023-09-06

Applicant: NVIDIA Corp.

Inventor： Shuo Zhang ,  Eric Zhu ,  Minto Zheng ,  Michael Zhai ,  Town Zhang ,  Jie Ma

IPC: H01L25/10 ,  H01L25/16 ,  H01L23/538 ,  H05K1/18

CPC classification number: H01L25/105 ,  H01L25/16 ,  H01L23/5386 ,  H05K1/181 ,  H01L2225/1094 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/10704 ,  H01L2225/107 ,  H05K2201/10015

Abstract: Layout techniques for circuits on substrates are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between circuits while simultaneously providing for the rapid provision of transient power demands to the circuits. The layout techniques may also enable improved thermal management for the circuits.

公开(公告)号：US20230197696A1

公开(公告)日：2023-06-22

申请号：US17553519

申请日：2021-12-16

Applicant: NVIDIA Corp.

Inventor： Shuo Zhang ,  Eric Zhu ,  Minto Zheng ,  Michael Zhai ,  Town Zhang ,  Jie Ma

IPC: H01L25/10 ,  H01L25/16 ,  H01L23/538 ,  H05K1/18

CPC classification number: H01L25/105 ,  H01L23/5386 ,  H01L25/16 ,  H05K1/181 ,  H01L2225/107 ,  H01L2225/1094 ,  H05K2201/10015 ,  H05K2201/10522 ,  H05K2201/10545 ,  H05K2201/10704

Abstract: Layout techniques for chip packages on printed circuit boards are disclosed that address the multivariate problem of minimizing routing distances for high-speed I/O pins between chip packages while simultaneously providing for the rapid provision of transient power demands to the chip packages. The layout techniques may also enable improved thermal management for the chip packages.

公开(公告)号：US20220199528A1

公开(公告)日：2022-06-23

申请号：US17128597

申请日：2020-12-21

Applicant: NVIDIA Corp.

Inventor： Jacky Qiu ,  Martin Ding ,  Jerry Zhou ,  Minto Zheng

IPC: H01L23/528 ,  H01L23/14 ,  H01L23/367 ,  H01L23/522 ,  H05K7/20 ,  H05K1/11 ,  H05K1/02

Abstract: A semiconductor assembly is described that includes a substrate having top and bottom sides. An integrated circuit die coupled to the substrate includes first and second distinct sets of ground pads. In some embodiments, the first and second sets of ground pads are configured to have distinct ground return paths to a host system. In further embodiments, one of the ground return paths may include a metal plate coupled between ground contacts on the top side of the substrate and ground contacts on a printed circuit board of the host system.