公开(公告)号：US11799799B2

公开(公告)日：2023-10-24

申请号：US17377943

申请日：2021-07-16

Applicant: NVIDIA Corp.

Inventor： Matthias Augustin Blumrich ,  Nan Jiang ,  Larry Robert Dennison

IPC: H04L29/08 ,  H04L49/101 ,  H04L49/00 ,  H04L49/9047 ,  H04L49/253

CPC classification number: H04L49/101 ,  H04L49/254 ,  H04L49/3036 ,  H04L49/70 ,  H04L49/9047

Abstract: A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery.

公开(公告)号：US11108704B2

公开(公告)日：2021-08-31

申请号：US16703697

申请日：2019-12-04

Applicant: NVIDIA Corp.

Inventor： Matthias Augustin Blumrich ,  Nan Jiang ,  Larry Robert Dennison

IPC: H04L29/08 ,  H04L12/933 ,  H04L12/935 ,  H04L12/861 ,  H04L12/937 ,  H04L12/931

Abstract: A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery.

公开(公告)号：US20200177521A1

公开(公告)日：2020-06-04

申请号：US16703697

申请日：2019-12-04

Applicant: NVIDIA Corp.

Inventor： Matthias Augustin Blumrich ,  Nan Jiang ,  Larry Robert Dennison

IPC: H04L12/933 ,  H04L12/935 ,  H04L12/931 ,  H04L12/937 ,  H04L12/861

Abstract: A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery.

公开(公告)号：US20200082246A1

公开(公告)日：2020-03-12

申请号：US16517431

申请日：2019-07-19

Applicant: NVIDIA Corp.

Inventor： Yakun Shao ,  Rangharajan Venkatesan ,  Nan Jiang ,  Brian Matthew Zimmer ,  Jason Clemons ,  Nathaniel Pinckney ,  Matthew R. Fojtik ,  William James Dally ,  Joel S. Emer ,  Stephen W. Keckler ,  Brucek Khailany

IPC: G06N3/04 ,  G06N3/08 ,  G06F9/54 ,  G06F9/445

Abstract: A distributed deep neural net (DNN) utilizing a distributed, tile-based architecture implemented on a semiconductor package. The package includes multiple chips, each with a central processing element, a global memory buffer, and processing elements. Each processing element includes a weight buffer, an activation buffer, and multiply-accumulate units to combine, in parallel, the weight values and the activation values.

公开(公告)号：US20250097153A1

公开(公告)日：2025-03-20

申请号：US18646410

申请日：2024-04-25

Applicant: NVIDIA Corp.

Inventor： John Martin Snyder ,  Nan Jiang ,  Dennis Charles Abts ,  Larry Robert Dennison

IPC: H04L47/122 ,  H04L47/125

Abstract: A process to manage congestion in a network involves converting traffic received from the local endpoints to a bandwidth demand for one or more destination endpoint in a remote group, and determining a sum over the destination endpoints of a minimum of a maximum bandwidth of a link and a bandwidth demand to one or more of the remote endpoints.

公开(公告)号：US11769040B2

公开(公告)日：2023-09-26

申请号：US16517431

申请日：2019-07-19

Applicant: NVIDIA Corp.

Inventor： Yakun Shao ,  Rangharajan Venkatesan ,  Nan Jiang ,  Brian Matthew Zimmer ,  Jason Clemons ,  Nathaniel Pinckney ,  Matthew R Fojtik ,  William James Dally ,  Joel S. Emer ,  Stephen W. Keckler ,  Brucek Khailany

IPC: G06F7/02 ,  G06N3/049 ,  G06F9/445 ,  G06F9/54 ,  G06N3/082

CPC classification number: G06N3/049 ,  G06F9/44505 ,  G06F9/544 ,  G06N3/082

Abstract: A distributed deep neural net (DNN) utilizing a distributed, tile-based architecture implemented on a semiconductor package. The package includes multiple chips, each with a central processing element, a global memory buffer, and processing elements. Each processing element includes a weight buffer, an activation buffer, and multiply-accumulate units to combine, in parallel, the weight values and the activation values.

公开(公告)号：US20210344616A1

公开(公告)日：2021-11-04

申请号：US17377943

申请日：2021-07-16

Applicant: NVIDIA Corp.

Inventor： Matthias Augustin Blumrich ,  Nan Jiang ,  Larry Robert Dennison

IPC: H04L12/933 ,  H04L12/935 ,  H04L12/861 ,  H04L12/937 ,  H04L12/931

Abstract: A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery.