公开(公告)号：US20220271951A1

公开(公告)日：2022-08-25

申请号：US17184396

申请日：2021-02-24

Applicant: NVIDIA Corp.

Inventor： Sudhir Shrikantha Kudva ,  Nikola Nedovic ,  Carl Thomas Gray

IPC: H04L9/32 ,  H04L9/08 ,  H03K19/17756 ,  H03K19/17704

Abstract: A circuit includes a set of multiple bit generating cells. One or more adjustable current sources is coupled to introduce perturbations into outputs of the bit generating cells. Based on the perturbations, the outputs of a subset less than all of the bit generating cells are selected, and applied as a control.

公开(公告)号：US11283349B2

公开(公告)日：2022-03-22

申请号：US16856884

申请日：2020-04-23

Applicant: NVIDIA Corp.

Inventor： Sudhir Shrikantha Kudva ,  Nikola Nedovic ,  Sanquan Song

IPC: H02M3/155

Abstract: This disclosure relates to current flattening circuits for an electrical load. The current flattening circuits incorporate randomize various parameters to add noise onto the supply current. This added noise may act to reduce the signal to noise ratio in the supply current, increasing the difficulty of identifying a computational artifact signal from power rail noise.

公开(公告)号：US11750192B2

公开(公告)日：2023-09-05

申请号：US17546438

申请日：2021-12-09

Applicant: NVIDIA Corp.

Inventor： Sudhir Shrikantha Kudva ,  Nikola Nedovic ,  Yan He

IPC: H03K19/003 ,  H03K19/0185

CPC classification number: H03K19/00315 ,  H03K19/018521

Abstract: Bit generating cells are subjected to processes that accelerate aging-related characteristics before they are configured for use in the field (enrolled). Aging improves the reliability of the cells by shifting device characteristic in a direction that improves the cell behavior with respect not only to aging but also environment variations. Outputs of the cells are read, and the cells are reconfigured with a bias to output an opposite value, and then aged for enrollment.

公开(公告)号：US11687679B2

公开(公告)日：2023-06-27

申请号：US18046275

申请日：2022-10-13

Applicant: NVIDIA Corp.

Inventor： Nikola Nedovic ,  Sudhir Shrikantha Kudva

IPC: G06F21/75 ,  H02M1/44 ,  H02M1/08 ,  H02M3/155

CPC classification number: G06F21/755 ,  H02M1/08 ,  H02M1/44 ,  H02M3/155

Abstract: Various implementations of a current flattening circuit are disclosed, including those utilizing a feedback current regulator, a feedforward current regulator, and a constant current source.

公开(公告)号：US11411563B1

公开(公告)日：2022-08-09

申请号：US17184396

申请日：2021-02-24

Applicant: NVIDIA Corp.

Inventor： Sudhir Shrikantha Kudva ,  Nikola Nedovic ,  Carl Thomas Gray

IPC: H03K19/17768 ,  H04L9/32 ,  H04L9/08 ,  H03K19/173 ,  H03K19/17748 ,  H03K19/17704 ,  H03K19/17756 ,  H03K19/177

Abstract: A circuit includes a set of multiple bit generating cells. One or more adjustable current sources is coupled to introduce perturbations into outputs of the bit generating cells. Based on the perturbations, the outputs of a subset less than all of the bit generating cells are selected, and applied as a control.

公开(公告)号：US20210083837A1

公开(公告)日：2021-03-18

申请号：US16927017

申请日：2020-07-13

Applicant: NVIDIA Corp.

Inventor： Xi Chen ,  Nikola Nedovic ,  Carl Thomas Gray ,  Stephen G Tell

IPC: H04L7/00

Abstract: A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction is computed as a global offset value based on a clock duty cycle error, combined with a local offset value for each data lane, and is applied to data receiver front ends.

公开(公告)号：US20210083836A1

公开(公告)日：2021-03-18

申请号：US16905635

申请日：2020-06-18

Applicant: NVIDIA Corp.

Inventor： Xi Chen ,  Nikola Nedovic ,  Carl Thomas Gray ,  Stephen G. Tell

IPC: H04L7/00 ,  H03K3/037 ,  H04B1/12 ,  H04B1/16

Abstract: A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction based on a clock duty cycle error is applied to data receiver front ends.

公开(公告)号：US10601324B1

公开(公告)日：2020-03-24

申请号：US16387383

申请日：2019-04-17

Applicant: NVIDIA Corp.

Inventor： Sudhir Shrikantha Kudva ,  Ahmed Abou-Alfotouh ,  Nikola Nedovic ,  John Poulton

IPC: H02M3/335 ,  H02M3/158

Abstract: A DC-DC converter circuit includes a switched tank converter configured to output a switching waveform. The DC-DC converter circuit further includes a transformer coupled to the switched tank converter to receive the switching waveform output by the switched tank converter across a primary winding of the transformer.

公开(公告)号：US20240161800A1

公开(公告)日：2024-05-16

申请号：US18056158

申请日：2022-11-16

Applicant: NVIDIA Corp.

Inventor： Mahmut Ersin Sinangil ,  Sudhir Shrikantha Kudva ,  Nikola Nedovic ,  Carl Thomas Gray

IPC: G11C7/24 ,  G11C7/10 ,  G11C7/20

CPC classification number: G11C7/24 ,  G11C7/1063 ,  G11C7/20

Abstract: PUF cells utilizing a dual-interlocking scheme demonstrating improved noise immunity and stability across different V/T conditions and different uses over time in noisy environments. The PUF cell may be advantageously utilized in conjunction with error detection techniques that screen out unstable cells. A set of such PUF cells utilized to generate a device-specific bit pattern, for example a master key.

公开(公告)号：US11594962B2

公开(公告)日：2023-02-28

申请号：US17580226

申请日：2022-01-20

Applicant: NVIDIA Corp.

Inventor： Sudhir Shrikantha Kudva ,  Nikola Nedovic ,  Sanquan Song

IPC: H02M3/155

Abstract: This disclosure relates to current flattening circuits for an electrical load. The current flattening circuits incorporate randomize various parameters to add noise onto the supply current. This added noise may act to reduce the signal to noise ratio in the supply current, increasing the difficulty of identifying a computational artifact signal from power rail noise.