公开(公告)号：US12009816B2

公开(公告)日：2024-06-11

申请号：US17932052

申请日：2022-09-14

Applicant: NVIDIA Corp.

Inventor： Walker Joseph Turner ,  John Poulton ,  Sanquan Song

IPC: H03K19/0185 ,  H03K3/037 ,  H03K19/00 ,  H03K3/356

CPC classification number: H03K19/018521 ,  H03K3/037 ,  H03K19/0013 ,  H03K19/018528 ,  H03K3/356165

Abstract: A level-shifting circuits utilizing storage cells for shifting signals low-to-high or high-to-low include control drivers with moving supply voltages. The moving supply voltages may power positive or negative supply terminals of the control drivers. The control drivers drive gates of common-source configured devices coupled to storage nodes of the storage cell.

公开(公告)号：US20240030917A1

公开(公告)日：2024-01-25

申请号：US17932075

申请日：2022-09-14

Applicant: NVIDIA Corp.

Inventor： Walker Joseph Turner ,  John Poulton ,  Sanquan Song

IPC: H03K19/0185 ,  H03K19/00

CPC classification number: H03K19/018521 ,  H03K19/0013 ,  H03K3/356165

Abstract: Stacked voltage domain level shifting circuits for shifting signals low-to-high or high-to-low include a storage cell and control drivers powered by a mid-range supply rail of the stacked voltage domain level shifting circuit, wherein the control drivers are coupled to drive common-source configured devices coupled to storage nodes of the storage cell.

公开(公告)号：US11632275B2

公开(公告)日：2023-04-18

申请号：US17243035

申请日：2021-04-28

Applicant: NVIDIA Corp.

Inventor： Sanquan Song ,  John Poulton

IPC: H04L25/34 ,  H04L25/49 ,  H04B1/00

Abstract: A transceiver circuit includes a receiver front end utilizing a ring oscillator, and a transmitter front end utilizing a pass-gate circuit in a first feedback path across a last-stage driver circuit. The transceiver circuit provides low impedance at low frequency and high impedance at high frequency, and desirable peaking behavior.

公开(公告)号：US11824533B1

公开(公告)日：2023-11-21

申请号：US17814752

申请日：2022-07-25

Applicant: NVIDIA Corp.

Inventor： Walker Joseph Turner ,  John Poulton ,  Sanquan Song

IPC: H03K19/0185 ,  H03K3/037

CPC classification number: H03K19/018528 ,  H03K3/037 ,  H03K19/018521

Abstract: Voltage level conversion circuits include PMOS pull-down devices or NMOS pull-up devices, and inverters with outputs that determine gate voltages of these devices. The inverters are powered by moving supply voltages, for example complementary supply voltages generated from a pair of cross-coupled inverters. The cross-coupled inverters may implement a data storage latch with the moving supply voltages generated from the internal data storage nodes of the latch.

公开(公告)号：US11594962B2

公开(公告)日：2023-02-28

申请号：US17580226

申请日：2022-01-20

Applicant: NVIDIA Corp.

Inventor： Sudhir Shrikantha Kudva ,  Nikola Nedovic ,  Sanquan Song

IPC: H02M3/155

Abstract: This disclosure relates to current flattening circuits for an electrical load. The current flattening circuits incorporate randomize various parameters to add noise onto the supply current. This added noise may act to reduce the signal to noise ratio in the supply current, increasing the difficulty of identifying a computational artifact signal from power rail noise.

公开(公告)号：US11936507B2

公开(公告)日：2024-03-19

申请号：US18182245

申请日：2023-03-10

Applicant: NVIDIA Corp.

Inventor： Sanquan Song ,  John Poulton

IPC: H04L25/34 ,  H04B1/00 ,  H04L25/49

CPC classification number: H04L25/4917 ,  H04B1/0082

Abstract: A transceiver circuit includes a receiver front end utilizing a ring oscillator, and a transmitter front end utilizing a pass-gate circuit in a first feedback path across a last-stage driver circuit. The transceiver circuit provides low impedance at low frequency and high impedance at high frequency, and desirable peaking behavior.

公开(公告)号：US20240030918A1

公开(公告)日：2024-01-25

申请号：US17932091

申请日：2022-09-14

Applicant: NVIDIA Corp.

Inventor： Walker Joseph Turner ,  John Poulton ,  Sanquan Song

IPC: H03K19/0185 ,  H03K19/00

CPC classification number: H03K19/018521 ,  H03K19/0013 ,  H03K3/356165

Abstract: Stacked voltage domain level shifting circuits for shifting signals low-to-high or high-to-low include a storage cell powered by a mid-range supply rail of the stacked voltage domain level shifting circuit, and control drivers powered by moving supply voltages generated by the storage cell, wherein the control drivers coupled to drive gates of common-source configured devices coupled to storage nodes of the storage cell.

公开(公告)号：US20220149728A1

公开(公告)日：2022-05-12

申请号：US17580226

申请日：2022-01-20

Applicant: NVIDIA Corp.

Inventor： Sudhir Shrikantha Kudva ,  Nikola Nedovic ,  Sanquan Song

IPC: H02M3/155

Abstract: This disclosure relates to current flattening circuits for an electrical load. The current flattening circuits incorporate randomize various parameters to add noise onto the supply current. This added noise may act to reduce the signal to noise ratio in the supply current, increasing the difficulty of identifying a computational artifact signal from power rail noise.

公开(公告)号：US10742224B2

公开(公告)日：2020-08-11

申请号：US16382050

申请日：2019-04-11

Applicant: NVIDIA Corp.

Inventor： Xi Chen ,  Sanquan Song

IPC: H03L7/099 ,  H03K3/03 ,  H03L7/07 ,  H03K5/133

Abstract: A circuit includes a first ring oscillator with a plurality of stages, each coupled via a voltage follower cross-coupling to a plurality of stages of a second ring oscillator. Further ring oscillators may be coupled to the first ring oscillator and the second ring oscillator. Additionally, the voltage follower cross-coupling for each of the stages may include one or more first voltage follower having a first strength, and one or more second voltage follower having a second strength different than the first strength.

公开(公告)号：US10581645B1

公开(公告)日：2020-03-03

申请号：US16427138

申请日：2019-05-30

Applicant: NVIDIA Corp.

Inventor： Sanquan Song ,  Nikola Nedovic

IPC: H04L25/03 ,  H03K19/0185 ,  H04B1/40 ,  H03F3/45

Abstract: A signal transceiver includes a signal transmitter driving a first differential link between a supply voltage of the signal transmitter and a fraction of the supply voltage, and driving a second differential link between the faction of the supply voltage and a reference ground. The signal transceiver also includes a signal receiver in which the first differential link is coupled to a gate node of an NMOS transistor and to a source node of a PMOS transistor; and the second differential link is coupled to a source node of the NMOS transistor and to a gate node of the PMOS transistor.