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公开(公告)号：US12131800B2
公开(公告)日：2024-10-29
申请号：US18056158
申请日：2022-11-16
Applicant: NVIDIA Corp.
Inventor： Mahmut Ersin Sinangil , Sudhir Shrikantha Kudva , Nikola Nedovic , Carl Thomas Gray
CPC classification number: G11C7/24 , G11C7/1063 , G11C7/20
Abstract: PUF cells utilizing a dual-interlocking scheme demonstrating improved noise immunity and stability across different V/T conditions and different uses over time in noisy environments. The PUF cell may be advantageously utilized in conjunction with error detection techniques that screen out unstable cells. A set of such PUF cells utilized to generate a device-specific bit pattern, for example a master key.
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公开(公告)号：US20220149728A1
公开(公告)日：2022-05-12
申请号：US17580226
申请日：2022-01-20
Applicant: NVIDIA Corp.
Inventor： Sudhir Shrikantha Kudva , Nikola Nedovic , Sanquan Song
IPC: H02M3/155
Abstract: This disclosure relates to current flattening circuits for an electrical load. The current flattening circuits incorporate randomize various parameters to add noise onto the supply current. This added noise may act to reduce the signal to noise ratio in the supply current, increasing the difficulty of identifying a computational artifact signal from power rail noise.
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公开(公告)号：US20250103076A1
公开(公告)日：2025-03-27
申请号：US18894507
申请日：2024-09-24
Applicant: NVIDIA Corp.
Inventor： Siddharth Saxena , Sudhir Shrikantha Kudva , Miguel Rodriguez , Vijay Srinivasan , Tezaswi Raja , Tom Gray , Santosh Santosh
Abstract: Reference voltage generators including a header circuit configured to pass current from a power supply to a time-to-digital converter, an amount of the current to pass determined by a thermometer code, and logic to update the thermometer code based on a comparison between an output of the time-to-digital converter and a digital code representing a reference voltage level.
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公开(公告)号：US20220271951A1
公开(公告)日：2022-08-25
申请号：US17184396
申请日：2021-02-24
Applicant: NVIDIA Corp.
Inventor： Sudhir Shrikantha Kudva , Nikola Nedovic , Carl Thomas Gray
IPC: H04L9/32 , H04L9/08 , H03K19/17756 , H03K19/17704
Abstract: A circuit includes a set of multiple bit generating cells. One or more adjustable current sources is coupled to introduce perturbations into outputs of the bit generating cells. Based on the perturbations, the outputs of a subset less than all of the bit generating cells are selected, and applied as a control.
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公开(公告)号：US11283349B2
公开(公告)日：2022-03-22
申请号：US16856884
申请日：2020-04-23
Applicant: NVIDIA Corp.
Inventor： Sudhir Shrikantha Kudva , Nikola Nedovic , Sanquan Song
IPC: H02M3/155
Abstract: This disclosure relates to current flattening circuits for an electrical load. The current flattening circuits incorporate randomize various parameters to add noise onto the supply current. This added noise may act to reduce the signal to noise ratio in the supply current, increasing the difficulty of identifying a computational artifact signal from power rail noise.
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Patent Agency Ranking
公开(公告)号：US11750192B2
公开(公告)日：2023-09-05
申请号：US17546438
申请日：2021-12-09
Applicant: NVIDIA Corp.
Inventor： Sudhir Shrikantha Kudva , Nikola Nedovic , Yan He
IPC: H03K19/003 , H03K19/0185
CPC classification number: H03K19/00315 , H03K19/018521
Abstract: Bit generating cells are subjected to processes that accelerate aging-related characteristics before they are configured for use in the field (enrolled). Aging improves the reliability of the cells by shifting device characteristic in a direction that improves the cell behavior with respect not only to aging but also environment variations. Outputs of the cells are read, and the cells are reconfigured with a bias to output an opposite value, and then aged for enrollment.
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公开(公告)号：US11687679B2
公开(公告)日：2023-06-27
申请号：US18046275
申请日：2022-10-13
Applicant: NVIDIA Corp.
Inventor： Nikola Nedovic , Sudhir Shrikantha Kudva
CPC classification number: G06F21/755 , H02M1/08 , H02M1/44 , H02M3/155
Abstract: Various implementations of a current flattening circuit are disclosed, including those utilizing a feedback current regulator, a feedforward current regulator, and a constant current source.
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公开(公告)号：US11411563B1
公开(公告)日：2022-08-09
申请号：US17184396
申请日：2021-02-24
Applicant: NVIDIA Corp.
Inventor： Sudhir Shrikantha Kudva , Nikola Nedovic , Carl Thomas Gray
IPC: H03K19/17768 , H04L9/32 , H04L9/08 , H03K19/173 , H03K19/17748 , H03K19/17704 , H03K19/17756 , H03K19/177
Abstract: A circuit includes a set of multiple bit generating cells. One or more adjustable current sources is coupled to introduce perturbations into outputs of the bit generating cells. Based on the perturbations, the outputs of a subset less than all of the bit generating cells are selected, and applied as a control.
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公开(公告)号：US10601324B1
公开(公告)日：2020-03-24
申请号：US16387383
申请日：2019-04-17
Applicant: NVIDIA Corp.
Inventor： Sudhir Shrikantha Kudva , Ahmed Abou-Alfotouh , Nikola Nedovic , John Poulton
Abstract: A DC-DC converter circuit includes a switched tank converter configured to output a switching waveform. The DC-DC converter circuit further includes a transformer coupled to the switched tank converter to receive the switching waveform output by the switched tank converter across a primary winding of the transformer.
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公开(公告)号：US20240161800A1
公开(公告)日：2024-05-16
申请号：US18056158
申请日：2022-11-16
Applicant: NVIDIA Corp.
Inventor： Mahmut Ersin Sinangil , Sudhir Shrikantha Kudva , Nikola Nedovic , Carl Thomas Gray
CPC classification number: G11C7/24 , G11C7/1063 , G11C7/20
Abstract: PUF cells utilizing a dual-interlocking scheme demonstrating improved noise immunity and stability across different V/T conditions and different uses over time in noisy environments. The PUF cell may be advantageously utilized in conjunction with error detection techniques that screen out unstable cells. A set of such PUF cells utilized to generate a device-specific bit pattern, for example a master key.
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