公开(公告)号：US12217151B2

公开(公告)日：2025-02-04

申请号：US18295145

申请日：2023-04-03

Applicant: NVIDIA Corp.

Inventor： Haoxing Ren ,  George Ferenc Kokai ,  Ting Ku ,  Walker Joseph Turner

IPC: G06F16/901 ,  G06F17/16 ,  G06F30/398 ,  G06N3/04 ,  G06N3/045 ,  G06N3/082

Abstract: A graph neural network to predict net parasitics and device parameters by transforming circuit schematics into heterogeneous graphs and performing predictions on the graphs. The system may achieve an improved prediction rate and reduce simulation errors.

公开(公告)号：US11804708B2

公开(公告)日：2023-10-31

申请号：US16812048

申请日：2020-03-06

Applicant: NVIDIA Corp.

Inventor： Jauwen Chen ,  Sunitha Venkataraman ,  Ting Ku

IPC: H02H9/04 ,  H01L27/02

CPC classification number: H02H9/046 ,  H01L27/0255 ,  H01L27/0277 ,  H01L27/0281

Abstract: An electrostatic discharge protection circuit is disclosed. It comprises a stacked drain-ballasted NMOS devices structure and a gate bias circuit. The gate bias circuit includes an inverter, a first gate bias output terminal, and a second gate bias output terminal. The first gate bias output terminal is coupled to a gate of a first one of the drain-ballasted NMOS devices. The second gate bias output terminal runs from an output of the inverter to a gate of a second one of the drain-ballasted NMOS devices.

公开(公告)号：US11651194B2

公开(公告)日：2023-05-16

申请号：US16859585

申请日：2020-04-27

Applicant: NVIDIA Corp.

Inventor： Haoxing Ren ,  George Kokai ,  Ting Ku ,  Walker Joseph Turner

IPC: G06F16/901 ,  G06F17/16 ,  G06N3/045

CPC classification number: G06N3/045 ,  G06F16/9024 ,  G06F17/16

Abstract: A graph neural network to predict net parasitics and device parameters by transforming circuit schematics into heterogeneous graphs and performing predictions on the graphs. The system may achieve an improved prediction rate and reduce simulation errors.

公开(公告)号：US20210281067A1

公开(公告)日：2021-09-09

申请号：US16812048

申请日：2020-03-06

Applicant: NVIDIA Corp.

Inventor： Jauwen Chen ,  Sunitha Venkataraman ,  Ting Ku

IPC: H02H9/04 ,  H01L27/02

Abstract: An electrostatic discharge protection circuit is disclosed. It comprises a stacked drain-ballasted NMOS devices structure and a gate bias circuit. The gate bias circuit includes an inverter, a first gate bias output terminal, and a second gate bias output terminal. The first gate bias output terminal is coupled to a gate of a first one of the drain-ballasted NMOS devices. The second gate bias output terminal runs from an output of the inverter to a gate of a second one of the drain-ballasted NMOS devices.

公开(公告)号：US20230237313A1

公开(公告)日：2023-07-27

申请号：US18295145

申请日：2023-04-03

Applicant: NVIDIA Corp.

Inventor： Haoxing Ren ,  George Ferenc Kokai ,  Ting Ku ,  Walker Joseph Turner

IPC: G06N3/045 ,  G06F16/901 ,  G06F17/16

CPC classification number: G06N3/045 ,  G06F16/9024 ,  G06F17/16

Abstract: A graph neural network to predict net parasitics and device parameters by transforming circuit schematics into heterogeneous graphs and performing predictions on the graphs. The system may achieve an improved prediction rate and reduce simulation errors.

公开(公告)号：US20210158127A1

公开(公告)日：2021-05-27

申请号：US16859585

申请日：2020-04-27

Applicant: NVIDIA Corp.

Inventor： Haoxing Ren ,  George Kokai ,  Ting Ku ,  Walker Joseph Turner

IPC: G06N3/04 ,  G06F17/16 ,  G06F16/901

Abstract: A graph neural network to predict net parasitics and device parameters by transforming circuit schematics into heterogeneous graphs and performing predictions on the graphs. The system may achieve an improved prediction rate and reduce simulation errors.