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公开(公告)号：US10999051B2
公开(公告)日：2021-05-04
申请号：US16905635
申请日：2020-06-18
Applicant: NVIDIA Corp.
Inventor： Xi Chen , Nikola Nedovic , Carl Thomas Gray , Stephen G Tell
Abstract: A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction based on a clock duty cycle error is applied to data receiver front ends.
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2.发明申请公开(公告)号：US20200162082A1
公开(公告)日：2020-05-21
申请号：US16382050
申请日：2019-04-11
Applicant: NVIDIA Corp.
Inventor： Xi Chen , Sanquan Song
Abstract: A circuit includes a first ring oscillator with a plurality of stages, each coupled via a voltage follower cross-coupling to a plurality of stages of a second ring oscillator. Further ring oscillators may be coupled to the first ring oscillator and the second ring oscillator. Additionally, the voltage follower cross-coupling for each of the stages may include one or more first voltage follower having a first strength, and one or more second voltage follower having a second strength different than the first strength.
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公开(公告)号：US12255675B2
公开(公告)日：2025-03-18
申请号：US17931472
申请日：2022-09-12
Applicant: NVIDIA Corp.
Inventor： Xi Chen , Yoshinori Nishi , John Poulton
Abstract: A simultaneous bi-directional (SBD) transceiver includes a main transmit driver, a replica transmit driver, and a series-series-bridged (SSB) tri-impedance network. A pre-driver stage includes parallel delay paths for the main transmit driver and the replica transmit driver, enabling the delay for signals received by the main transmit driver and the replica transmit driver to be independently configured.
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Patent Agency Ranking
4.发明公开公开(公告)号：US20230246661A1
公开(公告)日：2023-08-03
申请号：US17931472
申请日：2022-09-12
Applicant: NVIDIA Corp.
Inventor： Xi Chen , Yoshinori Nishi , John Poulton
CPC classification number: H04B1/0483 , H03H7/38 , H04B1/38
Abstract: A simultaneous bi-directional (SBD) transceiver includes a main transmit driver, a replica transmit driver, and a series-series-bridged (SSB) tri-impedance network. A pre-driver stage includes parallel delay paths for the main transmit driver and the replica transmit driver, enabling the delay for signals received by the main transmit driver and the replica transmit driver to be independently configured.
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5.发明授权公开(公告)号：US10742224B2
公开(公告)日：2020-08-11
申请号：US16382050
申请日：2019-04-11
Applicant: NVIDIA Corp.
Inventor： Xi Chen , Sanquan Song
Abstract: A circuit includes a first ring oscillator with a plurality of stages, each coupled via a voltage follower cross-coupling to a plurality of stages of a second ring oscillator. Further ring oscillators may be coupled to the first ring oscillator and the second ring oscillator. Additionally, the voltage follower cross-coupling for each of the stages may include one or more first voltage follower having a first strength, and one or more second voltage follower having a second strength different than the first strength.
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公开(公告)号：US10965440B1
公开(公告)日：2021-03-30
申请号：US16927017
申请日：2020-07-13
Applicant: NVIDIA Corp.
Inventor： Xi Chen , Nikola Nedovic , Carl Thomas Gray , Stephen G Tell
IPC: H04L7/00
Abstract: A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction is computed as a global offset value based on a clock duty cycle error, combined with a local offset value for each data lane, and is applied to data receiver front ends.
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公开(公告)号：US20210083837A1
公开(公告)日：2021-03-18
申请号：US16927017
申请日：2020-07-13
Applicant: NVIDIA Corp.
Inventor： Xi Chen , Nikola Nedovic , Carl Thomas Gray , Stephen G Tell
IPC: H04L7/00
Abstract: A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction is computed as a global offset value based on a clock duty cycle error, combined with a local offset value for each data lane, and is applied to data receiver front ends.
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公开(公告)号：US20210083836A1
公开(公告)日：2021-03-18
申请号：US16905635
申请日：2020-06-18
Applicant: NVIDIA Corp.
Inventor： Xi Chen , Nikola Nedovic , Carl Thomas Gray , Stephen G. Tell
Abstract: A receiver circuit includes a clock lane propagating a clock signal. A self-sampled clock applies a delayed version of the clock signal to the clock signal and compensation logic controls an amount of delay of the delayed version of the clock, based on a reference voltage offset (difference) between the receiver and a transmitter. The delayed version of the clock is centered on one unit interval of the clock. An offset correction based on a clock duty cycle error is applied to data receiver front ends.
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