公开(公告)号：US11663121B2

公开(公告)日：2023-05-30

申请号：US17531743

申请日：2021-11-20

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Chi She Chen ,  Jeffery C. Solomon ,  Mario Jesus Martinez ,  Hao Le ,  Soon J. Choi

IPC: G06F12/02 ,  G06F12/08 ,  G06F12/0871 ,  G06F3/06 ,  G11C7/10 ,  G06F13/28 ,  G06F13/10 ,  G06F12/06 ,  G06F12/0897

CPC classification number: G06F12/0246 ,  G06F3/061 ,  G06F3/068 ,  G06F3/0685 ,  G06F12/0638 ,  G06F12/08 ,  G06F12/0871 ,  G06F13/10 ,  G06F13/28 ,  G11C7/1072 ,  G06F3/0656 ,  G06F3/0688 ,  G06F12/0897 ,  G06F2206/1014 ,  G06F2212/205 ,  G06F2212/214 ,  G06F2212/313 ,  G06F2212/7201 ,  G06F2212/7208

Abstract: A memory module comprises a volatile memory subsystem including DRAM, a non-volatile memory subsystem including Flash memory, and a module control device. The Flash memory includes main Flash providing a main Flash memory space and scratch Flash providing a scratch Flash memory space. The module control device is configured to receive a request from the memory controller to move one or more segments of data in a first Flash block in the main Flash to the DRAM and to, for each respective segment of data: select a respective set of pages in the DRAM; transfer respective data stored in the respective set of pages from the DRAM to a corresponding segment in the scratch Flash; and transfer the respective segment of data to the respective set of pages in the DRAM. Thus, data can be moved segment by segment between the DRAM and the Flash memory.

公开(公告)号：US10380022B2

公开(公告)日：2019-08-13

申请号：US14536588

申请日：2014-11-07

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Chi She Chen ,  Jeffery C. Solomon ,  Mario Jesus Martinez ,  Hao Le ,  Soon J. Choi

IPC: G06F5/10 ,  G06F12/0871 ,  G06F3/06 ,  G06F12/0897 ,  G06F13/28

Abstract: A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller is configured to control intra-module data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller is further configured to monitor C/A signals on the C/A bus and schedule the intra-module data transfers in accordance with the C/A signals so that the intra-module data transfers do not conflict with accesses to the volatile memory subsystem by the memory controller.

公开(公告)号：US08864500B1

公开(公告)日：2014-10-21

申请号：US13653254

申请日：2012-10-16

Applicant: Netlist, Inc.

Inventor： Jayesh R. Bhakta ,  Enchao Yu ,  Chi She Chen ,  Richard E. Flaig

IPC: H01R12/00

CPC classification number: H05K1/147 ,  H01L2224/16225 ,  H01L2924/00011 ,  H01L2924/00014 ,  H05K1/0203 ,  H05K1/141 ,  H05K3/4691 ,  H05K2201/10159 ,  H05K2201/1056 ,  H05K2203/1572 ,  H01L2224/0401

Abstract: An electronic module for a computer system comprises a first circuit board having a plurality of edge connectors configured to releasably connect to electrical contacts of a computer system socket, a second circuit board having a plurality of contacts configured to connect with a plurality of electrical components, and a flexible portion having electrical conduits to provide electrical connection between the plurality of edge connectors and the plurality of contacts. The flexible portion further includes an electrically conductive layer extending across a region of the flexible portion. The electrically conductive layer is superposed with the electrical conduits and separated from electrical conduits by a dielectric layer.

Abstract translation: 一种用于计算机系统的电子模块，包括具有多个边缘连接器的第一电路板，所述多个边缘连接器被配置为可释放地连接到计算机系统插座的电触头，第二电路板具有被配置为与多个电气部件连接的多个触点， 以及具有电导管以在所述多个边缘连接器和所述多个触点之间提供电连接的柔性部分。 柔性部分还包括延伸穿过柔性部分的区域的导电层。 导电层与电导管叠合并通过电介质层与电导管分离。

公开(公告)号：US20220253380A1

公开(公告)日：2022-08-11

申请号：US17531743

申请日：2021-11-20

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Chi She Chen ,  Jeffery C. Solomon ,  Mario Jesus Martinez ,  Hao Le ,  Soon J. Choi

IPC: G06F12/02 ,  G06F12/08 ,  G06F12/0871 ,  G06F3/06 ,  G11C7/10 ,  G06F13/28 ,  G06F13/10 ,  G06F12/06

Abstract: A memory module comprises a volatile memory subsystem including DRAM, a non-volatile memory subsystem including Flash memory, and a module control device. The Flash memory includes main Flash providing a main Flash memory space and scratch Flash providing a scratch Flash memory space. The module control device is configured to receive a request from the memory controller to move one or more segments of data in a first Flash block in the main Flash to the DRAM and to, for each respective segment of data: select a respective set of pages in the DRAM; transfer respective data stored in the respective set of pages from the DRAM to a corresponding segment in the scratch Flash; and transfer the respective segment of data to the respective set of pages in the DRAM. Thus, data can be moved segment by segment between the DRAM and the Flash memory.

公开(公告)号：US11243886B2

公开(公告)日：2022-02-08

申请号：US16539895

申请日：2019-08-13

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R Bhakta ,  Chi She Chen ,  Jeffery C. Solomon ,  Mario Jesus Martinez ,  Hao Le ,  Soon J. Choi

IPC: G06F12/0871 ,  G06F3/06 ,  G06F12/0897 ,  G06F13/28

Abstract: A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller is configured to control intra-module data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller is further configured to monitor C/A signals on the C/A bus and schedule the intra-module data transfers in accordance with the C/A signals so that the intra-module data transfers do not conflict with accesses to the volatile memory subsystem by the memory controller.

公开(公告)号：US20230385192A1

公开(公告)日：2023-11-30

申请号：US18325081

申请日：2023-05-29

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Chi She Chen ,  Jeffery C. Solomon ,  Mario Jesus Martinez ,  Hao Le ,  Soon J. Choi

IPC: G06F12/02 ,  G06F12/08 ,  G06F12/0871 ,  G06F3/06 ,  G11C7/10 ,  G06F13/28 ,  G06F13/10 ,  G06F12/06

CPC classification number: G06F12/0246 ,  G06F12/08 ,  G06F12/0871 ,  G06F3/061 ,  G11C7/1072 ,  G06F13/28 ,  G06F3/068 ,  G06F3/0685 ,  G06F13/10 ,  G06F12/0638 ,  G06F2212/205 ,  G06F3/0688 ,  G06F12/0897

Abstract: A memory module comprises dynamic random access memory (DRAM), Flash memory, and a module controller. The module controller is configured to receive data to be transferred from the DRAM to the Flash memory, compute first cyclic redundancy check (CRC) codes for the data, and write the data into the Flash memory. The module controller is further configured to read the data from the Flash memory, compute second CRC codes for the data read from the Flash memory, and transfer the data to the DRAM. The module controller is further configured to compare the second CRC codes with the first CRC codes to determine one or more erroneous data bits in the data read from the Flash memory, read a data segment of the data from the DRAM that include the one or more erroneous data bits, correct the one or more erroneous data bits in the data segment, and write the data segment back into the DRAM.

公开(公告)号：US20200042456A1

公开(公告)日：2020-02-06

申请号：US16539895

申请日：2019-08-13

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Chi She Chen ,  Jeffery C. Solomon ,  Mario Jesus Martinez ,  Hao Le ,  Soon J. Choi

IPC: G06F12/0871

Abstract: A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller is configured to control intra-module data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller is further configured to monitor C/A signals on the C/A bus and schedule the intra-module data transfers in accordance with the C/A signals so that the intra-module data transfers do not conflict with accesses to the volatile memory subsystem by the memory controller.

公开(公告)号：US20150169238A1

公开(公告)日：2015-06-18

申请号：US14536588

申请日：2014-11-07

Applicant: Netlist, Inc.

Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Chi She Chen ,  Jeffery C. Solomon ,  Mario Jesus Martinez ,  Hao Le ,  Soon J. Choi

IPC: G06F3/06

CPC classification number: G06F12/0871 ,  G06F3/0656 ,  G06F3/0688 ,  G06F12/0897 ,  G06F13/28 ,  G06F2206/1014 ,  G06F2212/214 ,  G06F2212/313 ,  G06F2212/7201 ,  G06F2212/7208

Abstract: A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller is configured to control intra-module data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller is further configured to monitor C/A signals on the C/A bus and schedule the intra-module data transfers in accordance with the C/A signals so that the intra-module data transfers do not conflict with accesses to the volatile memory subsystem by the memory controller.

Abstract translation: 存储器模块包括被配置为耦合到计算机系统中的存储器通道并且能够用作计算机系统的主存储器的非易失性存储器子系统，为计算机系统提供存储的非易失性存储器子系统，以及耦合到 易失性存储器子系统，非易失性存储器子系统和C / A总线。 模块控制器被配置为控制易失性存储器子系统和非易失性存储器子系统之间的模块内数据传输。 模块控制器还被配置为监视C / A总线上的C / A信号，并根据C / A信号调度模块内数据传输，使得模块内数据传输不与对易失性的访问冲突 内存子系统由内存控制器。

公开(公告)号：US08971045B1

公开(公告)日：2015-03-03

申请号：US13731014

申请日：2012-12-30

Applicant: NETLIST, Inc.

Inventor： Robert S. Pauley ,  Jayesh R. Bhakta ,  William M. Gervasi ,  Chi She Chen ,  Jose Delvalle

IPC: H05K7/20 ,  H05K1/02

CPC classification number: H05K1/0203 ,  H05K1/144 ,  H05K2201/10189 ,  H05K2201/1056 ,  H05K2201/2018 ,  Y10T29/49117 ,  Y10T29/49124 ,  Y10T29/4913

Abstract: A module is electrically connectable to a computer system. The module includes an edge connector with a plurality of electrical contacts electrically connectable to the computer system, at least one layer of thermally conductive material thermally coupled to the edge connector, and first and second printed circuit boards each having a plurality of integrated circuit components that are electrically coupled to the edge connector and thermally coupled to the at least one layer of thermally conductive material. The at least one layer of thermally conductive material are disposed between the first and second printed circuit boards.

Abstract translation: 模块可电连接到计算机系统。 模块包括边缘连接器，其具有可电连接到计算机系统的多个电触点，热耦合到边缘连接器的至少一层导热材料，以及第一和第二印刷电路板，每个具有多个集成电路部件， 电耦合到边缘连接器并且热耦合到至少一个导热材料层。 至少一层导热材料设置在第一和第二印刷电路板之间。