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    Hybrid memory module and system and method of operating the same
    2.
    发明授权
    Hybrid memory module and system and method of operating the same 有权

    公开(公告)号：US11243886B2

    公开(公告)日：2022-02-08

    申请号：US16539895

    申请日：2019-08-13

    Applicant: Netlist, Inc.

    Inventor： Hyun Lee ,  Jayesh R Bhakta ,  Chi She Chen ,  Jeffery C. Solomon ,  Mario Jesus Martinez ,  Hao Le ,  Soon J. Choi

    IPC: G06F12/0871 ,  G06F3/06 ,  G06F12/0897 ,  G06F13/28

    Abstract: A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller is configured to control intra-module data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller is further configured to monitor C/A signals on the C/A bus and schedule the intra-module data transfers in accordance with the C/A signals so that the intra-module data transfers do not conflict with accesses to the volatile memory subsystem by the memory controller.

    HYBRID MEMORY MODULE AND SYSTEM AND METHOD OF OPERATING THE SAME
    4.
    发明申请
    HYBRID MEMORY MODULE AND SYSTEM AND METHOD OF OPERATING THE SAME 审中-公开

    公开(公告)号：US20200042456A1

    公开(公告)日：2020-02-06

    申请号：US16539895

    申请日：2019-08-13

    Applicant: Netlist, Inc.

    Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Chi She Chen ,  Jeffery C. Solomon ,  Mario Jesus Martinez ,  Hao Le ,  Soon J. Choi

    IPC: G06F12/0871

    Abstract: A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller is configured to control intra-module data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller is further configured to monitor C/A signals on the C/A bus and schedule the intra-module data transfers in accordance with the C/A signals so that the intra-module data transfers do not conflict with accesses to the volatile memory subsystem by the memory controller.

    HYBRID MEMORY MODULE AND SYSTEM AND METHOD OF OPERATING THE SAME
    5.
    发明申请
    HYBRID MEMORY MODULE AND SYSTEM AND METHOD OF OPERATING THE SAME 审中-公开
    混合存储器模块及其操作方法

    公开(公告)号：US20150169238A1

    公开(公告)日：2015-06-18

    申请号：US14536588

    申请日：2014-11-07

    Applicant: Netlist, Inc.

    Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Chi She Chen ,  Jeffery C. Solomon ,  Mario Jesus Martinez ,  Hao Le ,  Soon J. Choi

    IPC: G06F3/06

    CPC classification number: G06F12/0871 ,  G06F3/0656 ,  G06F3/0688 ,  G06F12/0897 ,  G06F13/28 ,  G06F2206/1014 ,  G06F2212/214 ,  G06F2212/313 ,  G06F2212/7201 ,  G06F2212/7208

    Abstract: A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller is configured to control intra-module data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller is further configured to monitor C/A signals on the C/A bus and schedule the intra-module data transfers in accordance with the C/A signals so that the intra-module data transfers do not conflict with accesses to the volatile memory subsystem by the memory controller.

    Abstract translation: 存储器模块包括被配置为耦合到计算机系统中的存储器通道并且能够用作计算机系统的主存储器的非易失性存储器子系统，为计算机系统提供存储的非易失性存储器子系统，以及耦合到 易失性存储器子系统，非易失性存储器子系统和C / A总线。 模块控制器被配置为控制易失性存储器子系统和非易失性存储器子系统之间的模块内数据传输。 模块控制器还被配置为监视C / A总线上的C / A信号，并根据C / A信号调度模块内数据传输，使得模块内数据传输不与对易失性的访问冲突 内存子系统由内存控制器。

    Memory module with circuit providing load isolation and noise reduction
    7.
    发明授权
    Memory module with circuit providing load isolation and noise reduction 有权
    具有电路的存储器模块，提供负载隔离和降噪

    公开(公告)号：US09037809B1

    公开(公告)日：2015-05-19

    申请号：US14324990

    申请日：2014-07-07

    Applicant: Netlist, Inc.

    Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Jeffrey C. Solomon ,  Mario Jesus Martinez ,  Chi-She Chen

    IPC: G06F12/00 ,  G11C5/02

    CPC classification number: G06F13/1684 ,  G06F13/4027 ,  G11C5/02 ,  G11C5/06 ,  G11C8/18 ,  H05K1/0216 ,  H05K1/0243 ,  H05K2201/10053 ,  H05K2201/10159 ,  H05K2201/10189

    Abstract: Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.

    Abstract translation: 本文描述的某些实施例包括具有印刷电路板的存储器模块，该印刷电路板包括被配置为可操作地耦合到计算机系统的存储器控​​制器的至少一个连接器。 存储器模块还包括印刷电路板上的多个存储器件和包括可操作地耦合到至少一个存储器件的第一组端口的电路。 电路还包括可操作地耦合到至少一个连接器的第二组端口。 电路包括切换电路，其被配置为选择性地将第二组端口的一个或多个端口耦合到第一组端口的一个或多个端口。 第一组和第二组的每个端口包括校正电路，其减少在第一组端口和第二组端口之间传输的一个或多个信号中的噪声。

    Hybrid memory module and system and method of operating the same
    9.
    发明授权
    Hybrid memory module and system and method of operating the same 有权

    公开(公告)号：US10380022B2

    公开(公告)日：2019-08-13

    申请号：US14536588

    申请日：2014-11-07

    Applicant: Netlist, Inc.

    Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Chi She Chen ,  Jeffery C. Solomon ,  Mario Jesus Martinez ,  Hao Le ,  Soon J. Choi

    IPC: G06F5/10 ,  G06F12/0871 ,  G06F3/06 ,  G06F12/0897 ,  G06F13/28

    Abstract: A memory module comprises a volatile memory subsystem configured to coupled to a memory channel in computer system and capable of serving as main memory for the computer system, a non-volatile memory subsystem providing storage for the computer system, and a module controller coupled to the volatile memory subsystem, the non-volatile memory subsystem, and the C/A bus. The module controller is configured to control intra-module data transfers between the volatile memory subsystem and the non-volatile memory subsystem. The module controller is further configured to monitor C/A signals on the C/A bus and schedule the intra-module data transfers in accordance with the C/A signals so that the intra-module data transfers do not conflict with accesses to the volatile memory subsystem by the memory controller.

    Memory module and circuit providing load isolation and noise reduction
    10.
    发明授权
    Memory module and circuit providing load isolation and noise reduction 有权

    公开(公告)号：US10025731B1

    公开(公告)日：2018-07-17

    申请号：US14715491

    申请日：2015-05-18

    Applicant: Netlist, Inc.

    Inventor： Hyun Lee ,  Jayesh R. Bhakta ,  Jeffrey C. Solomon ,  Mario Jesus Martinez ,  Chi-She Chen

    IPC: G06F12/00 ,  G06F13/16 ,  G11C5/02 ,  G11C5/06 ,  G11C8/18 ,  G06F13/40

    Abstract: Certain embodiments described herein include a memory module having a printed circuit board including at least one connector configured to be operatively coupled to a memory controller of a computer system. The memory module further includes a plurality of memory devices on the printed circuit board and a circuit including a first set of ports operatively coupled to at least one memory device. The circuit further includes a second set of ports operatively coupled to the at least one connector. The circuit includes a switching circuit configured to selectively operatively couple one or more ports of the second set of ports to one or more ports of the first set of ports. Each port of the first set and the second set comprises a correction circuit which reduces noise in one or more signals transmitted between the first set of ports and the second set of ports.

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