公开(公告)号：US07895421B2

公开(公告)日：2011-02-22

申请号：US11776986

申请日：2007-07-12

Applicant: Nhon Quach ,  Sean Lie

Inventor： Nhon Quach ,  Sean Lie

IPC: G06F9/44

CPC classification number: G06F11/3419 ,  G06F11/3466 ,  G06F2201/88 ,  G06F2201/885

Abstract: A system and method of accounting for lost clock cycles in a microprocessor. A method includes detecting a first reason which prevents exit of an entry from an instruction retirement queue, and incrementing a first count corresponding to the first reason, wherein the first count is incremented while the first reason prevents exit of the entry from the queue. A first point in time is determined when said first reason no longer prevents exit of the entry from the queue. A second reason which prevents exit of the entry from the queue is detected, wherein the second reason came into existence prior to said first point in time. A second count corresponding to the second reason is incremented, wherein incrementing the second count begins at the first point in time.

Abstract translation: 一种考虑微处理器中丢失时钟周期的系统和方法。 一种方法包括检测防止条目从指令退出队列退出的第一原因，并且增加与第一原因相对应的第一计数，其中第一计数增加，而第一原因阻止该条目从队列退出。 当第一个原因不再阻止条目退出队列时，确定第一时间点。 检测到防止条目从队列中退出的第二个原因，其中第二原因在所述第一时间点之前存在。 对应于第二原因的第二计数增加，其中增加第二计数从第一时间点开始。

公开(公告)号：US06625756B1

公开(公告)日：2003-09-23

申请号：US09469961

申请日：1999-12-21

Applicant: Edward T. Grochowski ,  William Rash ,  Nhon Quach

Inventor： Edward T. Grochowski ,  William Rash ,  Nhon Quach

IPC: G06F1100

CPC classification number: G06F9/3885 ,  G06F9/28 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3861 ,  G06F11/1407 ,  G06F11/1641 ,  G06F11/1658 ,  G06F2201/845

Abstract: A processor is provided that implements a replay mechanism to recover from soft errors. The processor includes a protected execution unit, a check unit to detect errors in results generated by the protected execution unit, and a replay unit to track selected instructions issued to the protected execution unit. When the check unit detects an error, it triggers the replay unit to reissue the selected instructions to the protected execution unit. One embodiment of the replay unit provides an instruction buffer that includes pointers to track issue and retirement status of in-flight instructions. When the check unit indicates an error, the replay unit resets a pointer to reissue the instruction for which the error was detected.

Abstract translation: 提供了一种处理器，其实现了从软错误中恢复的重放机制。 处理器包括受保护的执行单元，用于检测由受保护的执行单元产生的结果中的错误的检查单元，以及用于跟踪发送给受保护的执行单元的选定指令的重放单元。 当检查单元检测到错误时，它触发重放单元将所选择的指令重新发送到受保护的执行单元。 重放单元的一个实施例提供指令缓冲器，其包括跟踪飞行中指令的发行和退休状态的指针。 当检查单元指示错误时，重放单元重置指针以重新发出检测到错误的指令。

公开(公告)号：US20090183035A1

公开(公告)日：2009-07-16

申请号：US11972166

申请日：2008-01-10

Applicant: Michael G. Butler ,  Nhon Quach

Inventor： Michael G. Butler ,  Nhon Quach

IPC: G06F9/302 ,  G06F11/14

CPC classification number: G06F11/1497 ,  G06F11/1405 ,  G06F11/1641 ,  G06F11/1645

Abstract: A processor core includes an instruction decode unit that may dispatch a same integer instruction stream to a plurality of integer execution units and may consecutively dispatch a same floating-point instruction stream to a floating-point unit. The integer execution units may operate in lock-step such that during each clock cycle, each respective integer execution unit executes the same integer instruction. The floating-point unit may execute the same floating-point instruction stream twice. Prior to the integer instructions retiring, compare logic may detect a mismatch between execution results from each of the integer execution units. In addition, prior to the results of the floating-point instruction stream transferring out of the floating-point unit, the compare logic may also detect a mismatch between results of execution of each consecutive floating-point instruction stream. Further, in response to detecting any mismatch, the compare logic may cause instructions causing the mismatch to be re-executed.

Abstract translation: 处理器核心包括指令解码单元，其可以向多个整数执行单元分派相同的整数指令流，并且可以将相同的浮点指令流连续地分派到浮点单元。 整数执行单元可以锁定步骤操作，使得在每个时钟周期期间，每个相应的整数执行单元执行相同的整数指令。 浮点单元可以执行相同的浮点指令流两次。 在整数指令退出之前，比较逻辑可以检测来自每个整数执行单元的执行结果之间的不匹配。 此外，在浮点指令流从浮点单元传出的结果之前，比较逻辑还可以检测每个连续浮点指令流的执行结果之间的不匹配。 此外，响应于检测到任何不匹配，比较逻辑可能导致导致不匹配的指令被重新执行。

公开(公告)号：US20090019317A1

公开(公告)日：2009-01-15

申请号：US11776986

申请日：2007-07-12

Applicant: Nhon Quach ,  Sean Lie

Inventor： Nhon Quach ,  Sean Lie

IPC: G06F11/34

CPC classification number: G06F11/3419 ,  G06F11/3466 ,  G06F2201/88 ,  G06F2201/885

Abstract: A system and method of accounting for lost clock cycles in a microprocessor. A method includes detecting a first reason which prevents exit of an entry from an instruction retirement queue, and incrementing a first count corresponding to the first reason, wherein the first count is incremented while the first reason prevents exit of the entry from the queue. A first point in time is determined when said first reason no longer prevents exit of the entry from the queue. A second reason which prevents exit of the entry from the queue is detected, wherein the second reason came into existence prior to said first point in time. A second count corresponding to the second reason is incremented, wherein incrementing the second count begins at the first point in time.

Abstract translation: 一种考虑微处理器中丢失时钟周期的系统和方法。 一种方法包括检测防止条目从指令退出队列退出的第一原因，并且增加与第一原因相对应的第一计数，其中第一计数增加，而第一原因阻止该条目从队列退出。 当第一个原因不再阻止条目退出队列时，确定第一时间点。 检测到防止条目从队列中退出的第二个原因，其中第二原因在所述第一时间点之前存在。 对应于第二原因的第二计数增加，其中增加第二计数从第一时间点开始。

公开(公告)号：US06636991B1

公开(公告)日：2003-10-21

申请号：US09470970

申请日：1999-12-23

Applicant: Nhon Quach

Inventor： Nhon Quach

IPC: G06F1100

CPC classification number: G06F11/10 ,  G06F11/0724 ,  G06F11/0772 ,  G06F11/0781

Abstract: A signaling mechanism associated with errors in a processor is promoted or demoted based on a set of stored values.

Abstract translation: 基于一组存储值来升级或降级与处理器中的错误相关联的信令机制。

公开(公告)号：US06625749B1

公开(公告)日：2003-09-23

申请号：US09469963

申请日：1999-12-21

Applicant: Nhon Quach

Inventor： Nhon Quach

IPC: G06F1100

CPC classification number: G06F11/1641 ,  G06F11/165 ,  G06F11/1658 ,  G06F11/1679 ,  G06F2201/845

Abstract: A computer system includes processor having dual execution cores and a non-volatile memory that stores an error recovery routine. The processor's execution cores operate in lock step when the processor is in a redundant execution mode, and they operate independently when the processor is in a split execution mode. The error recovery routine is invoked when the processor detects a soft error while operating in the redundant execution mode. The error recovery routine switches the processor to split execution mode. In split mode, each execution core saves uncorrupted processor state data to a designated memory location and updates any corrupted data with corresponding processor state data from the other execution core. The error recovery routine returns the processor to redundant mode, initializes each execution core with the recovered processor state data, and returns control of the processor to the program thread that was executing when the soft error was detected.

Abstract translation: 计算机系统包括具有双执行核心的处理器和存储错误恢复例程的非易失性存储器。 当处理器处于冗余执行模式时，处理器的执行核心以锁定步骤运行，并且当处理器处于分离执行模式时，它们独立运行。 当处理器在冗余执行模式下运行时检测到软错误时，会调用错误恢复程序。 错误恢复程序将处理器切换到分割执行模式。 在分离模式下，每个执行核心将未处理的处理器状态数据保存到指定的存储器位置，并使用来自其他执行核心的相应处理器状态数据更新任何损坏的数据。 错误恢复程序将处理器返回到冗余模式，用恢复的处理器状态数据初始化每个执行核心，并将处理器的控制权返回到检测到软错误时执行的程序线程。

公开(公告)号：US07865770B2

公开(公告)日：2011-01-04

申请号：US11972171

申请日：2008-01-10

Applicant: Nhon Quach

Inventor： Nhon Quach

IPC: G06F11/00

CPC classification number: G06F9/3885 ,  G06F9/30189 ,  G06F9/3851 ,  G06F9/3857 ,  G06F9/3861 ,  G06F9/3891

Abstract: A processor core includes an instruction decode unit that may dispatch a same integer instruction stream to a plurality of integer execution units operating in lock-step. The processor core also includes signature generation logic that may generate, concurrently with execution of the integer instructions, a respective signature from result signals conveyed on respective result buses in one or more pipeline stages within each of the integer execution units in response to the result signals becoming available. The processor core also includes compare logic that may detect a mismatch between signatures from each of the integer execution units. Further, in response to the compare logic detecting any mismatch, the compare logic may cause instructions causing the mismatch to be re-executed.

Abstract translation: 处理器核心包括指令解码单元，其可以将相同的整数指令流分派到以锁定步骤操作的多个整数执行单元。 处理器核心还包括签名生成逻辑，其可以与执行整数指令同时地生成来自在每个整数执行单元内的一个或多个流水线级中的相应结果总线上传送的响应于结果信号的相应签名 变得可用 处理器核心还包括可以检测来自每个整数执行单元的签名之间的不匹配的比较逻辑。 此外，响应于比较逻辑检测到任何不匹配，比较逻辑可能导致导致不匹配的指令被重新执行。

公开(公告)号：US07340643B2

公开(公告)日：2008-03-04

申请号：US10653785

申请日：2003-09-02

Applicant: Edward T. Grochowski ,  William Rash ,  Nhon Quach

Inventor： Edward T. Grochowski ,  William Rash ,  Nhon Quach

IPC: G06F11/00

CPC classification number: G06F9/3885 ,  G06F9/28 ,  G06F9/3836 ,  G06F9/3857 ,  G06F9/3861 ,  G06F11/1407 ,  G06F11/1641 ,  G06F11/1658 ,  G06F2201/845

Abstract: A processor is provided that implements a replay mechanism to recover from soft errors. The processor includes a protected execution unit, a check unit to detect errors in results generated by the protected execution unit, and a replay unit to track selected instructions issued to the protected execution unit. When the check unit detects an error, it triggers the replay unit to reissue the selected instructions to the protected execution unit. One embodiment of the replay unit provides an instruction buffer that includes pointers to track issue and retirement status of in-flight instructions. When the check unit indicates an error, the replay unit resets a pointer to reissue the instruction for which the error was detected.

Abstract translation: 提供了一种处理器，其实现了从软错误中恢复的重放机制。 处理器包括受保护的执行单元，用于检测由受保护的执行单元产生的结果中的错误的检查单元，以及用于跟踪发送给受保护的执行单元的选定指令的重放单元。 当检查单元检测到错误时，它触发重放单元将所选择的指令重新发送到受保护的执行单元。 重放单元的一个实施例提供指令缓冲器，其包括跟踪飞行中指令的发行和退休状态的指针。 当检查单元指示错误时，重放单元重置指针以重新发出检测到错误的指令。

公开(公告)号：US07315920B2

公开(公告)日：2008-01-01

申请号：US11028293

申请日：2005-01-04

Applicant: Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

Inventor： Nhon Quach ,  John Crawford ,  Greg S. Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

IPC: G06F12/00

CPC classification number: G06F12/0891

Abstract: The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory including an input conversion circuit to receive a 1-hot vector and to convert the 1-hot vector to a 2-hot vector. The tag array memory also including a memory array coupled to the input conversion circuit, the memory array to store the 2-hot vector; and an output conversion circuit coupled to the memory array, the output conversion circuit to receive the 2-hot vector and to convert the 2-hot vector back to the 1-hot vector.

Abstract translation: 本发明涉及高度可靠的高性能微处理器的设计，更具体地说涉及使用高速缓存存储器保护方案（例如，1加热有效位方案和2热向量高速缓存方案）的设计。 这些保护方案保护缓存中标签阵列中使用的1-hot向量，并设计为提供硬件节省，以更高的速度运行并且易于实现。 根据本发明的一个实施例，一种标签阵列存储器，包括一个输入转换电路，用于接收1个热矢量，并将该1个热矢量转换为2个热矢量。 标签阵列存储器还包括耦合到输入转换电路的存储器阵列，存储器阵列以存储2-热矢量; 以及耦合到存储器阵列的输出转换电路，所述输出转换电路接收所述2-热矢量并将所述2-热矢量转换回所述1-热矢量。

公开(公告)号：US20050120184A1

公开(公告)日：2005-06-02

申请号：US11028293

申请日：2005-01-04

Applicant: Nhon Quach ,  John Crawford ,  Greg Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

Inventor： Nhon Quach ,  John Crawford ,  Greg Mathews ,  Edward Grochowski ,  Chakravarthy Kosaraju

IPC: G06F12/08 ,  G06F12/00

CPC classification number: G06F12/0891

Abstract: The present invention relates to the design of highly reliable high performance microprocessors, and more specifically to designs that use cache memory protection schemes such as, for example, a 1-hot plus valid bit scheme and a 2-hot vector cache scheme. These protection schemes protect the 1-hot vectors used in the tag array in the cache and are designed to provide hardware savings, operate at higher speeds and be simple to implement. In accordance with an embodiment of the present invention, a tag array memory including an input conversion circuit to receive a 1-hot vector and to convert the 1-hot vector to a 2-hot vector. The tag array memory also including a memory array coupled to the input conversion circuit, the memory array to store the 2-hot vector; and an output conversion circuit coupled to the memory array, the output conversion circuit to receive the 2-hot vector and to convert the 2-hot vector back to the 1-hot vector.

Abstract translation: 本发明涉及高度可靠的高性能微处理器的设计，更具体地说涉及使用高速缓存存储器保护方案（例如，1加热有效位方案和2热向量高速缓存方案）的设计。 这些保护方案保护缓存中标签阵列中使用的1-hot向量，并设计为提供硬件节省，以更高的速度运行并且易于实现。 根据本发明的一个实施例，一种标签阵列存储器，包括一个输入转换电路，用于接收1个热矢量，并将该1个热矢量转换为2个热矢量。 标签阵列存储器还包括耦合到输入转换电路的存储器阵列，存储器阵列以存储2-热矢量; 以及耦合到存储器阵列的输出转换电路，所述输出转换电路接收所述2-热矢量并将所述2-热矢量转换回所述1-热矢量。