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    OBFUSCATING ANALOG CIRCUITS USING SWITCHED PHASE CIRCUITS
    1.
    发明申请
    OBFUSCATING ANALOG CIRCUITS USING SWITCHED PHASE CIRCUITS 有权

    公开(公告)号：US20240427942A1

    公开(公告)日：2024-12-26

    申请号：US18744204

    申请日：2024-06-14

    Applicant: Northeastern University

    Inventor： Aatmesh Shrivastava

    IPC: G06F21/70

    Abstract: Methods, systems, and computer program products are presented herein for obfuscating analog circuits using switched phase circuits. In particular, methods, systems, and computer program products using a Switch Mode Time Domain Locking (SMDL) scheme, presented herein, may be used to protect analog circuits. A first input signal to an analog circuit is generated. The first input signal comprises a reference phase. The analog circuit is adapted to perform a predetermined function. A second input signal to the analog circuit is generated. The second input signal comprises a provided phase. Enablement of the predetermined function of the analog circuit is toggled based on alignment of the reference phase and the provided phase.

    BEAMFORMING WIRELESS POWER TRANSFER SCHEME
    3.
    发明申请
    BEAMFORMING WIRELESS POWER TRANSFER SCHEME 有权

    公开(公告)号：US20230026315A1

    公开(公告)日：2023-01-26

    申请号：US17861603

    申请日：2022-07-11

    Applicant: Northeastern University

    Inventor： Aatmesh Shrivastava

    IPC: H02J50/20 ,  H02J50/40 ,  H02J50/80 ,  H01Q3/22

    Abstract: Wireless power transfer (WPT) efficiency is enhanced using an ultra-low power (ULP) distributed beamforming technique. A phase and frequency offset correction technique is used for beam-forming optimization, a backscattering communication technique is used to reduce power over-head, and a new rectifier and MPT method is used for high efficiency RF-to-DC conversion.

    ULTRA-LOW POWER TEMPERATURE SENSOR DESIGN
    4.
    发明申请
    ULTRA-LOW POWER TEMPERATURE SENSOR DESIGN 有权

    公开(公告)号：US20250088192A1

    公开(公告)日：2025-03-13

    申请号：US18825626

    申请日：2024-09-05

    Applicant: Northeastern University

    Inventor： Aatmesh Shrivastava

    IPC: H03L1/02 ,  G05F3/30 ,  H03M1/46

    Abstract: Methods, systems, and computer products are presented herein for determining temperature using ultra-low power temperature sensing systems. An ultra-low power (ULP) temperature sensing system comprises a proportional to absolute temperature (PTAT) current source, a switched-capacitor converter electrically coupled to the PTAT current source, and a ULP analog-to-digital converter (ADC) electrically coupled to the PTAT current source and the switched-capacitor converter. The PTAT current source is configured to generate a PTAT current that varies with an operating temperature. The switched-capacitor converter is configured to generate an analog voltage signal based on the PTAT current. The ULP ADC is configured to output a digital voltage value corresponding to the analog voltage signal.

    ULTRA-LOW POWER TIMING CIRCUIT WITH PLL LOCKING
    5.
    发明申请
    ULTRA-LOW POWER TIMING CIRCUIT WITH PLL LOCKING 有权

    公开(公告)号：US20250088177A1

    公开(公告)日：2025-03-13

    申请号：US18825616

    申请日：2024-09-05

    Applicant: Northeastern University

    Inventor： Aatmesh Shrivastava

    IPC: H03K3/011 ,  H03K5/135 ,  H03L7/099

    Abstract: Methods, systems, and computer program products are presented herein for circuit timing using ultra-low power (ULP) timing circuit systems. A ULP timing circuit system comprises a receiver circuit, phase lock loop (PLL) circuit, crystal oscillator (XO) circuit, temperature sensing and calibration circuit, and temperature compensation circuit. The receiver circuit is configured to receive a reference clock signal. The XO circuit is configured to produce an output clock signal. The PLL circuit is configured to produce a control signal based on the reference clock signal and output clock signal. The temperature compensation circuit is configured to produce a compensation signal based on an operating temperature. The temperature sensing and calibration circuit is configured to sense the operating temperature and to calibrate the XO circuit based on the operating temperature, control signal, and compensation signal to lock a frequency of the output clock signal to the reference clock signal.

    ULTRA LOW POWER WAKE UP RADIO ARCHITECTURE
    7.
    发明公开
    ULTRA LOW POWER WAKE UP RADIO ARCHITECTURE 审中-公开

    公开(公告)号：US20240089018A1

    公开(公告)日：2024-03-14

    申请号：US18274304

    申请日：2022-01-19

    Applicant: Northeastern University

    Inventor： Aatmesh Shrivastava ,  Ankit Mittal

    IPC: H04B17/318 ,  H03G3/30

    CPC classification number: H04B17/318 ,  H03G3/3052

    Abstract: A radio frequency (RF) signal strength detection technique is disclosed with a received signal strength indicator (RSSI) circuit, which can be deployed in an internet-of-things (IoT) network. The RSSI circuit is based on a direct conversion of RF to digital code indicating the signal strength. The direct conversion is achieved by the repeated switching of a rectifier's output voltage using an ultra-low power comparator. A 5-bit programmable feedback circuit can be used to correct detection inaccuracies. The RSSI circuit can be implemented in a 65-nm CMOS process and consumes 15 nW power. It can have a linear dynamic range of 26 dB and exhibit an error of ±0.5 dB with a wide bandwidth of 500 MHz. The technique has been verified with simulation and measurement results. The high detection accuracy with ultra-low power consumption of the proposed RSSI circuit is favorable for IoT applications including, e.g., biomedical, localization, and other low-power applications.

    HIGH EFFICIENCY POWER OBFUSCATION SWITCHED CAPACITOR DC-DC CONVERTER ARCHITECTURE
    9.
    发明申请
    HIGH EFFICIENCY POWER OBFUSCATION SWITCHED CAPACITOR DC-DC CONVERTER ARCHITECTURE 有权

    公开(公告)号：US20220302830A1

    公开(公告)日：2022-09-22

    申请号：US17697087

    申请日：2022-03-17

    Applicant: Northeastern University

    Inventor： Aatmesh Shrivastava ,  Nikita Mirchandani

    IPC: H02M3/07 ,  H04L9/06

    Abstract: Side channel attacks (SCA) such as correlation power analysis (CPA) have been demonstrated to be very effective in breaking cryptographic engines. The inherent dependence of the power consumption on the secret key can be exploited by statistical analysis to retrieve the key. Various embodiments disclosed herein relate to a new power obfuscation switched capacitor (POSC) DC-DC converter design, which can conceal the leakage of information through power consumption. It works by adding an extra phase to the conventional two-phase switched capacitor (SC) converter, during which a part of the charge from the flying capacitor is extracted and stored on a storage capacitor. This guarantees that the same amount of charge is drawn from the input power supply in each cycle. The design was successfully evaluated by analyzing the power supply to an Advanced Encryption Standard (AES) unit powered by the converter.

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