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公开(公告)号：US10233559B2
公开(公告)日：2019-03-19
申请号：US15350636
申请日：2016-11-14
Applicant: Northeastern University
Inventor： Asli Sirman , Ahmed Busnaina , Cihan Yilmaz , Jun Huang , Sivasubramanian Somu
IPC: C25D13/22 , H05K1/03 , H05K1/09 , H05K3/12 , C25D13/12 , C25D13/04 , C25D13/20 , C09D5/44 , C09D125/06 , B82Y40/00 , H05K1/02 , H01L21/02 , H01L29/06 , B82Y30/00
Abstract: A method for high rate assembly of nanoelements into two-dimensional void patterns on a non-conductive substrate surface utilizes an applied electric field to stabilize against forces resulting from pulling the substrate through the surface of a nanoelement suspension. The electric field contours emanating from a conductive layer in the substrate, covered by an insulating layer, are modified by a patterned photoresist layer, resulting in an increased driving force for nanoelements to migrate from a liquid suspension to voids on a patterned substrate having a non-conductive surface. The method can be used for the production of microscale and nanoscale circuits, sensors, and other electronic devices.
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公开(公告)号：US20190211467A1
公开(公告)日：2019-07-11
申请号：US16358324
申请日：2019-03-19
Applicant: Northeastern University
Inventor： Asli Sirman , Ahmed Busnaina , Cihan Yilmaz , Jun Huang , Sivasubramanian Somu
IPC: C25D13/22 , H05K1/09 , C25D13/04 , C09D5/44 , H05K3/12 , C25D13/20 , C09D125/06 , B82Y40/00 , H05K1/02 , C25D13/12 , H05K1/03
CPC classification number: C25D13/22 , B82Y30/00 , B82Y40/00 , C09D5/4407 , C09D5/4488 , C09D125/06 , C25D13/04 , C25D13/12 , C25D13/20 , H01L21/0243 , H01L21/0259 , H01L21/02628 , H01L29/0665 , H05K1/0213 , H05K1/0306 , H05K1/092 , H05K3/1258 , Y10S977/882 , Y10S977/892
Abstract: A method for high rate assembly of nanoelements into two-dimensional void patterns on a non-conductive substrate surface utilizes an applied electric field to stabilize against forces resulting from pulling the substrate through the surface of a nanoelement suspension. The electric field contours emanating from a conductive layer in the substrate, covered by an insulating layer, are modified by a patterned photoresist layer, resulting in an increased driving force for nanoelements to migrate from a liquid suspension to voids on a patterned substrate having a non-conductive surface. The method can be used for the production of microscale and nanoscale circuits, sensors, and other electronic devices.
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公开(公告)号：US20190161883A1
公开(公告)日：2019-05-30
申请号：US16243832
申请日：2019-01-09
Applicant: Northeastern University
Inventor： Ahmed Busnaina , Hanchul Cho , Sivasubramanian Somu , Jun Huang
Abstract: Damascene templates have two-dimensionally patterned raised metal features disposed on an underlying conductive layer extending across a substrate. The templates are topographically flat overall, and the patterned conductive features establish micron-scale and nanometer-scale patterns for the assembly of nanoelements into nanoscale circuits and sensors. The templates are made using microfabrication techniques together with chemical mechanical polishing. These templates are compatible with various directed assembly techniques, including electrophoresis, and offer essentially 100% efficient assembly and transfer of nanoelements in a continuous operation cycle. The templates can be repeatedly used for transfer of patterned nanoelements thousands of times with minimal or no damage, and the transfer process involves no intermediate processes between cycles. The assembly and transfer processes employed are carried out at room temperature and pressure and are thus amenable to low cost, high-rate device production.
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公开(公告)号：US10208394B2
公开(公告)日：2019-02-19
申请号：US15180262
申请日：2016-06-13
Applicant: Northeastern University
Inventor： Ahmed Busnaina , Hanchul Cho , Sivasubramanian Somu , Jun Huang
Abstract: Damascene templates have two-dimensionally patterned raised metal features disposed on an underlying conductive layer extending across a substrate. The templates are topographically flat overall, and the patterned conductive features establish micron-scale and nanometer-scale patterns for the assembly of nanoelements into nanoscale circuits and sensors. The templates are made using microfabrication techniques together with chemical mechanical polishing. These templates are compatible with various directed assembly techniques, including electrophoresis, and offer essentially 100% efficient assembly and transfer of nanoelements in a continuous operation cycle. The templates can be repeatedly used for transfer of patterned nanoelements thousands of times with minimal or no damage, and the transfer process involves no intermediate processes between cycles. The assembly and transfer processes employed are carried out at room temperature and pressure and are thus amenable to low cost, high-rate device production.
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5.发明申请High Rate Electric Field Driven Nanoelement Assembly on an Insulated Surface 审中-公开绝缘表面高速电场驱动的纳米元件组件公开(公告)号：US20170058422A1
公开(公告)日：2017-03-02
申请号：US15350636
申请日：2016-11-14
Applicant: Northeastern University
Inventor： Asli Sirman , Ahmed Busnaina , Cihan Yilmaz , Jun Huang , Sivasubramanian Somu
IPC: C25D13/22 , H05K1/09 , H05K3/12 , C09D125/06 , C25D13/04 , C25D13/20 , C09D5/44 , H05K1/03 , C25D13/12
CPC classification number: C25D13/22 , B82Y30/00 , B82Y40/00 , C09D5/4407 , C09D5/4488 , C09D125/06 , C25D13/04 , C25D13/12 , C25D13/20 , H01L21/0243 , H01L21/0259 , H01L21/02628 , H01L29/0665 , H05K1/0213 , H05K1/0306 , H05K1/092 , H05K3/1258 , Y10S977/882 , Y10S977/892
Abstract: A method for high rate assembly of nanoelements into two-dimensional void patterns on a non-conductive substrate surface utilizes an applied electric field to stabilize against forces resulting from pulling the substrate through the surface of a nanoelement suspension. The electric field contours emanating from a conductive layer in the substrate, covered by an insulating layer, are modified by a patterned photoresist layer, resulting in an increased driving force for nanoelements to migrate from a liquid suspension to voids on a patterned substrate having a non-conductive surface. The method can be used for the production of microscale and nanoscale circuits, sensors, and other electronic devices.
Abstract translation: 将纳米元件高速组装成非导电基底表面上的二维空穴图案的方法利用施加的电场来抵抗通过纳米元素悬浮液的表面拉动基底所产生的力。 由绝缘层覆盖的衬底中的导电层发出的电场轮廓由图案化的光致抗蚀剂层改变，导致纳米元件从液体悬浮液迁移到具有非绝缘层的图案化衬底上的空隙的驱动力增加， 导电表面。 该方法可用于生产微尺度和纳米级电路，传感器和其他电子设备。
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Patent Agency Ranking
6.发明申请公开(公告)号：US20170009365A1
公开(公告)日：2017-01-12
申请号：US15180262
申请日：2016-06-13
Applicant: Northeastern University
Inventor： Ahmed Busnaina , Hanchul Cho , Sivasubramanian Somu , Jun Huang
CPC classification number: C25D13/02 , B82B3/0042 , B82Y10/00 , B82Y40/00 , C25D13/00 , C25D15/00 , G03F7/0002 , Y10S977/882
Abstract: Damascene templates have two-dimensionally patterned raised metal features disposed on an underlying conductive layer extending across a substrate. The templates are topographically flat overall, and the patterned conductive features establish micron-scale and nanometer-scale patterns for the assembly of nanoelements into nanoscale circuits and sensors. The templates are made using microfabrication techniques together with chemical mechanical polishing. These templates are compatible with various directed assembly techniques, including electrophoresis, and offer essentially 100% efficient assembly and transfer of nanoelements in a continuous operation cycle. The templates can be repeatedly used for transfer of patterned nanoelements thousands of times with minimal or no damage, and the transfer process involves no intermediate processes between cycles. The assembly and transfer processes employed are carried out at room temperature and pressure and are thus amenable to low cost, high-rate device production.
Abstract translation: 镶嵌模板具有二维图案化的凸起金属特征，其设置在跨越衬底延伸的下面的导电层上。 模板在整体上在地形上平坦，并且图案化的导电特征建立了用于将纳米元件组装成纳米尺度电路和传感器的微米级和纳米级图案。 模板使用微加工技术和化学机械抛光制成。 这些模板与各种定向组装技术（包括电泳）兼容，并且在连续的操作循环中提供基本上100％的有效组装和转移纳米元件。 可以重复使用模板，以最小或无损伤的方式传输图案化纳米元件数千次，并且转印过程不涉及循环之间的中间过程。 所采用的组装和转移方法在室温和压力下进行，因此可以实现低成本，高速率的装置生产。
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公开(公告)号：US09365946B2
公开(公告)日：2016-06-14
申请号：US14356328
申请日：2012-11-08
Applicant: Northeastern University
Inventor： Ahmed Busnaina , Hanchul Cho , Sivasubramanian Somu , Jun Huang
CPC classification number: C25D13/02 , B82B3/0042 , B82Y10/00 , B82Y40/00 , C25D13/00 , C25D15/00 , G03F7/0002 , Y10S977/882
Abstract: Damascene templates have two-dimensionally patterned raised metal features disposed on an underlying conductive layer extending across a substrate. The templates are topographically flat overall, and the patterned conductive features establish micron-scale and nanometer-scale patterns for the assembly of nanoelements into nanoscale circuits and sensors. The templates are made using microfabrication techniques together with chemical mechanical polishing. These templates are compatible with various directed assembly techniques, including electrophoresis, and offer essentially 100% efficient assembly and transfer of nanoelements in a continuous operation cycle. The templates can be repeatedly used for transfer of patterned nanoelements thousands of times with minimal or no damage, and the transfer process involves no intermediate processes between cycles. The assembly and transfer processes employed are carried out at room temperature and pressure and are thus amenable to low cost, high-rate device production.
Abstract translation: 镶嵌模板具有二维图案化的凸起金属特征，其设置在跨越衬底延伸的下面的导电层上。 模板在整体上在地形上平坦，并且图案化的导电特征建立了用于将纳米元件组装成纳米尺度电路和传感器的微米级和纳米级图案。 模板使用微加工技术和化学机械抛光制成。 这些模板与各种定向组装技术（包括电泳）兼容，并且在连续的操作循环中提供基本上100％的有效组装和转移纳米元件。 可以重复使用模板，以最小或无损伤的方式传输图案化纳米元件数千次，并且转印过程不涉及循环之间的中间过程。 所采用的组装和转移方法在室温和压力下进行，因此可以实现低成本，高速率的装置生产。
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8.发明申请公开(公告)号：US20160021738A1
公开(公告)日：2016-01-21
申请号：US14838930
申请日：2015-08-28
Applicant: Northeastern University
Inventor： Asli Sirman , Ahmed Busnaina , Cihan Yilmaz , Jun Huang , Sivasubramanian Somu
CPC classification number: C25D13/22 , B82Y30/00 , B82Y40/00 , C09D5/4407 , C09D5/4488 , C09D125/06 , C25D13/04 , C25D13/12 , C25D13/20 , H01L21/0243 , H01L21/0259 , H01L21/02628 , H01L29/0665 , H05K1/0213 , H05K1/0306 , H05K1/092 , H05K3/1258 , Y10S977/882 , Y10S977/892
Abstract: A method for high rate assembly of nanoelements into two-dimensional void patterns on a non-conductive substrate surface utilizes an applied electric field to stabilize against forces resulting from pulling the substrate through the surface of a nanoelement suspension. The electric field contours emanating from a conductive layer in the substrate, covered by an insulating layer, are modified by a patterned photoresist layer, resulting in an increased driving force for nanoelements to migrate from a liquid suspension to voids on a patterned substrate having a non-conductive surface. The method can be used for the production of microscale and nanoscale circuits, sensors, and other electronic devices.
Abstract translation: 将纳米元件高速组装成非导电基底表面上的二维空穴图案的方法利用施加的电场来抵抗通过纳米元素悬浮液的表面拉动基底所产生的力。 由绝缘层覆盖的衬底中的导电层发出的电场轮廓由图案化的光致抗蚀剂层改变，导致纳米元件从液体悬浮液迁移到具有非绝缘层的图案化衬底上的空隙的驱动力增加， 导电表面。 该方法可用于生产微尺度和纳米级电路，传感器和其他电子设备。
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公开(公告)号：US09497855B2
公开(公告)日：2016-11-15
申请号：US14838930
申请日：2015-08-28
Applicant: Northeastern University
Inventor： Asli Sirman , Ahmed Busnaina , Cihan Yilmaz , Jun Huang , Sivasubramanian Somu
IPC: H05K1/03 , H05K1/09 , B82Y40/00 , C25D13/04 , C25D13/12 , H05K1/02 , H01L21/02 , H01L29/06 , B82Y30/00
CPC classification number: C25D13/22 , B82Y30/00 , B82Y40/00 , C09D5/4407 , C09D5/4488 , C09D125/06 , C25D13/04 , C25D13/12 , C25D13/20 , H01L21/0243 , H01L21/0259 , H01L21/02628 , H01L29/0665 , H05K1/0213 , H05K1/0306 , H05K1/092 , H05K3/1258 , Y10S977/882 , Y10S977/892
Abstract: A method for high rate assembly of nanoelements into two-dimensional void patterns on a non-conductive substrate surface utilizes an applied electric field to stabilize against forces resulting from pulling the substrate through the surface of a nanoelement suspension. The electric field contours emanating from a conductive layer in the substrate, covered by an insulating layer, are modified by a patterned photoresist layer, resulting in an increased driving force for nanoelements to migrate from a liquid suspension to voids on a patterned substrate having a non-conductive surface. The method can be used for the production of microscale and nanoscale circuits, sensors, and other electronic devices.
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公开(公告)号：US10815582B2
公开(公告)日：2020-10-27
申请号：US16243832
申请日：2019-01-09
Applicant: Northeastern University
Inventor： Ahmed Busnaina , Hanchul Cho , Sivasubramanian Somu , Jun Huang
Abstract: Damascene templates have two-dimensionally patterned raised metal features disposed on an underlying conductive layer extending across a substrate. The templates are topographically flat overall, and the patterned conductive features establish micron-scale and nanometer-scale patterns for the assembly of nanoelements into nanoscale circuits and sensors. The templates are made using microfabrication techniques together with chemical mechanical polishing. These templates are compatible with various directed assembly techniques, including electrophoresis, and offer essentially 100% efficient assembly and transfer of nanoelements in a continuous operation cycle. The templates can be repeatedly used for transfer of patterned nanoelements thousands of times with minimal or no damage, and the transfer process involves no intermediate processes between cycles. The assembly and transfer processes employed are carried out at room temperature and pressure and are thus amenable to low cost, high-rate device production.
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