公开(公告)号：US11315898B2

公开(公告)日：2022-04-26

申请号：US16622161

申请日：2018-06-06

Applicant: OSRAM OLED GmbH

Inventor： Klaus Mueller ,  Andreas Ploessl ,  Mathias Wendt

IPC: H01L23/00

Abstract: A method for fastening a semiconductor chip on a substrate and an electronic component are disclosed. In an embodiment a method includes providing a semiconductor chip, applying a solder metal layer sequence on the semiconductor chip, providing a substrate, applying a metallization layer sequence on the substrate, applying the semiconductor chip on the substrate via the solder metal layer sequence and the metallization layer sequence and heating the applied semiconductor chip on the substrate for fastening the semiconductor chip on the substrate. The solder metal layer may include a first metallic layer comprising an indium-tin alloy, a barrier layer arranged above the first metallic layer and a second metallic layer comprising gold arranged between the barrier layer and the semiconductor chip, wherein an amount of substance of the gold in the second metallic layer is greater than an amount of substance of tin in the first metallic layer.

公开(公告)号：US11961820B2

公开(公告)日：2024-04-16

申请号：US16768208

申请日：2019-02-05

Applicant: OSRAM OLED GmbH

Inventor： Simeon Katz ,  Mathias Wendt ,  Sophia Huppmann ,  Marcus Zenger ,  Jens Mueller

IPC: H01L23/00 ,  H01L33/62

CPC classification number: H01L24/89 ,  H01L24/05 ,  H01L24/08 ,  H01L33/62 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/05582 ,  H01L2224/05611 ,  H01L2224/05644 ,  H01L2224/08111 ,  H01L2224/08146 ,  H01L2224/08502 ,  H01L2224/80805 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/12041 ,  H01L2933/0066

Abstract: A method for producing a connection between component parts and a component made of component parts are disclosed. In an embodiment, a includes providing a first component part having a first exposed insulation layer and a second component part having a second exposed insulation layer, wherein each of the insulation layers has at least one opening, joining together the first and second component parts such that the opening of the first insulation layer and the opening of the second insulation layer overlap in top view, wherein an Au layer and a Sn layer are arranged one above the other in at least one of the openings and melting the Au layer and the Sn layer to form an AuSn alloy, wherein the AuSn alloy forms a through-via after cooling electrically conductively connecting the first component part to the second component part.

公开(公告)号：US20210327725A1

公开(公告)日：2021-10-21

申请号：US17361435

申请日：2021-06-29

Applicant: OSRAM OLED GmbH

Inventor： Mathias Wendt ,  Andreas Weimar

IPC: H01L21/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00

Abstract: An electronic component includes a lead frame; a semiconductor chip arranged above the lead frame; and a connection layer sequence arranged between the lead frame and the semiconductor chip, wherein the connection layer sequence includes a first intermetallic layer including gold and indium or gold, indium and tin, a second intermetallic layer including indium and a titanium compound, indium and nickel, indium and platinum or indium and titanium, and a third intermetallic layer including indium and gold.

公开(公告)号：US11094559B2

公开(公告)日：2021-08-17

申请号：US16604252

申请日：2018-04-18

Applicant: OSRAM OLED GmbH

Inventor： Mathias Wendt ,  Andreas Weimar

IPC: H01L21/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L21/60

Abstract: A method of attaching a semiconductor chip on a lead frame includes A) providing a semiconductor chip, B) applying a solder metal layer sequence to the semiconductor chip, wherein the solder metal layer sequence includes a first metallic layer including indium or an indium-tin alloy, C) providing a lead frame, D) applying a metallization layer sequence to the lead frame, wherein the metallization layer sequence includes a fourth layer including indium and/or tin arranged above the lead frame and a third layer including gold arranged above the fourth layer, E) forming an intermetallic intermediate layer including gold and indium, gold and tin or gold, tin and indium, G) applying the semiconductor chip to the lead frame via the solder metal layer sequence and the intermetallic intermediate layer, and H) heating the arrangement produced in G) to attach the semiconductor chip to the lead frame.

公开(公告)号：US20200294962A1

公开(公告)日：2020-09-17

申请号：US16768208

申请日：2019-02-05

Applicant: OSRAM OLED GmbH

Inventor： Simeon Katz ,  Mathias Wendt ,  Sophia Huppmann ,  Marcus Zenger ,  Jens Mueller

IPC: H01L23/00 ,  H01L33/62

Abstract: A method for producing a connection between component parts and a component made of component parts are disclosed. In an embodiment, a includes providing a first component part having a first exposed insulation layer and a second component part having a second exposed insulation layer, wherein each of the insulation layers has at least one opening, joining together the first and second component parts such that the opening of the first insulation layer and the opening of the second insulation layer overlap in top view, wherein an Au layer and a Sn layer are arranged one above the other in at least one of the openings and melting the Au layer and the Sn layer to form an AuSn alloy, wherein the AuSn alloy forms a through-via after cooling electrically conductively connecting the first component part to the second component part.

公开(公告)号：US20200211997A1

公开(公告)日：2020-07-02

申请号：US16622161

申请日：2018-06-06

Applicant: OSRAM OLED GmbH

Inventor： Klaus Mueller ,  Andreas Ploessl ,  Mathias Wendt

IPC: H01L23/00

Abstract: A method for fastening a semiconductor chip on a substrate and an electronic component are disclosed. In an embodiment a method includes providing a semiconductor chip, applying a solder metal layer sequence on the semiconductor chip, providing a substrate, applying a metallization layer sequence on the substrate, applying the semiconductor chip on the substrate via the solder metal layer sequence and the metallization layer sequence and heating the applied semiconductor chip on the substrate for fastening the semiconductor chip on the substrate. The solder metal layer may include a first metallic layer comprising an indium-tin alloy, a barrier layer arranged above the first metallic layer and a second metallic layer comprising gold arranged between the barrier layer and the semiconductor chip, wherein an amount of substance of the gold in the second metallic layer is greater than an amount of substance of tin in the first metallic layer.

公开(公告)号：US11545369B2

公开(公告)日：2023-01-03

申请号：US17361435

申请日：2021-06-29

Applicant: OSRAM OLED GmbH

Inventor： Mathias Wendt ,  Andreas Weimar

IPC: H01L21/48 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L21/60

Abstract: An electronic component includes a lead frame; a semiconductor chip arranged above the lead frame; and a connection layer sequence arranged between the lead frame and the semiconductor chip, wherein the connection layer sequence includes a first intermetallic layer including gold and indium or gold, indium and tin, a second intermetallic layer including indium and a titanium compound, indium and nickel, indium and platinum or indium and titanium, and a third intermetallic layer including indium and gold.

公开(公告)号：US20220208715A1

公开(公告)日：2022-06-30

申请号：US17699719

申请日：2022-03-21

Applicant: OSRAM OLED GmbH

Inventor： Klaus Mueller ,  Andreas Ploessl ,  Mathias Wendt

IPC: H01L23/00

Abstract: In an embodiment a method includes providing a semiconductor chip, applying a solder metal layer sequence on the semiconductor chip, providing a substrate, applying a metallization layer sequence on the substrate, applying the semiconductor chip on the substrate via the solder metal layer sequence and the metallization layer sequence and heating the applied semiconductor chip on the substrate for fastening the semiconductor chip on the substrate, wherein the solder metal layer sequence includes a first metallic layer including an indium-tin alloy, a barrier layer arranged above the first metallic layer, and a second metallic layer having gold arranged between the barrier layer and the semiconductor chip, and wherein the indium-tin alloy has the following formula: InxSn1-x with 0.04≤x≤0.2.