公开(公告)号：US20230037782A1

公开(公告)日：2023-02-09

申请号：US17460274

申请日：2021-08-29

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yi-Hsiang MA ,  Szu-Wei Chen ,  Yu-Hung Lin ,  An-Cheng Liu

IPC: G06N3/08 ,  G06N3/04 ,  G06K9/62 ,  G06T5/50

Abstract: A method for training an asymmetric generative adversarial network to generate an image and an electronic apparatus using the same are provided. The method includes the following. A first real image belonging to a first category, a second real image belonging to a second category and a third real image belonging to a third category are input to an asymmetric generative adversarial network for training the asymmetric generative adversarial network, and the asymmetric generative adversarial network includes a first generator, a second generator, a first discriminator and a second discriminator. A fourth real image belonging to the second category is input to the first generator in the trained asymmetric generative adversarial network to generate a defect image.

公开(公告)号：US20220365706A1

公开(公告)日：2022-11-17

申请号：US17336347

申请日：2021-06-02

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Siang Yang ,  Wei Lin ,  Shih-Jia Zeng ,  An-Cheng Liu ,  Yu-Cheng Hsu

IPC: G06F3/06

Abstract: A data accessing method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a codeword stored in a physical programming unit, and calculating a bit change ratio of a bit value change in dummy data included in the codeword; adjusting a read voltage level or a log likelihood ratio according to the bit change ratio; and performing a decoding operation on the codeword by using the adjusted read voltage level or the adjusted log likelihood ratio.

公开(公告)号：US20210082522A1

公开(公告)日：2021-03-18

申请号：US16601517

申请日：2019-10-14

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  An-Cheng Liu ,  Szu-Wei Chen ,  Yu-Siang Yang

IPC: G11C16/26 ,  H03M7/42 ,  G11C11/56

Abstract: A voltage identifying method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a plurality of first memory cells according to a first read voltage group in a plurality of read voltage groups and performing a first decoding operation to generate first verification information; identifying a plurality of second read voltage groups in the plurality of read voltage groups corresponding to a first interval in a plurality of intervals according to the first interval in which the first verification information is located; and reading the plurality of first memory cells by using a third read voltage group in the plurality of second read voltage groups and performing the first decoding operation.

公开(公告)号：US10978163B2

公开(公告)日：2021-04-13

申请号：US16601517

申请日：2019-10-14

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  An-Cheng Liu ,  Szu-Wei Chen ,  Yu-Siang Yang

IPC: G11C16/26 ,  G11C11/56 ,  H03M7/42

Abstract: A voltage identifying method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a plurality of first memory cells according to a first read voltage group in a plurality of read voltage groups and performing a first decoding operation to generate first verification information; identifying a plurality of second read voltage groups in the plurality of read voltage groups corresponding to a first interval in a plurality of intervals according to the first interval in which the first verification information is located; and reading the plurality of first memory cells by using a third read voltage group in the plurality of second read voltage groups and performing the first decoding operation.

公开(公告)号：US20200168289A1

公开(公告)日：2020-05-28

申请号：US16251105

申请日：2019-01-18

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  An-Cheng Liu ,  Yu-Cheng Hsu ,  Yu-Siang Yang

IPC: G11C29/50 ,  G06F3/06 ,  G11C29/12 ,  G11C29/14

Abstract: A memory control method for a rewritable non-volatile memory module including a plurality of physical units is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first physical unit of a rewritable non-volatile memory module; decoding the first data by a decoding circuit; updating reliability information according to the decoded first data; reading second data from a second physical unit of the rewritable non-volatile memory module; and decoding the second data by the decoding circuit according to the updated reliability information.

公开(公告)号：US20200034232A1

公开(公告)日：2020-01-30

申请号：US16120314

申请日：2018-09-03

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  An-Cheng Liu ,  Yu-Siang Yang ,  Yu-Cheng Hsu

IPC: G06F11/10 ,  G11C29/52 ,  H03M13/45

Abstract: A bit determining method, a memory control circuit unit and a memory storage device are provided. The method includes: reading a first storage state of a first memory cell to obtain a first value of a first significant bit; reading the first storage state of the first memory cell to obtain at least one second value of at least one second significant bit; performing a first decoding operation according to the at least one second value to obtain at least one third value of the decoded second significant bit; determining whether the first significant bit is a special bit according to the first storage state and a second storage state corresponding to the at least one third value; and if the first significant bit is the special bit, performing a corresponding decoding operation.

公开(公告)号：US20190163363A1

公开(公告)日：2019-05-30

申请号：US15867719

申请日：2018-01-11

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  An-Cheng Liu ,  Lih Yuarn Ou ,  Szu-Wei Chen

IPC: G06F3/06 ,  G11C16/26 ,  G06F11/10 ,  G11C29/52

CPC classification number: G06F3/061 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/1072 ,  G11C16/0483 ,  G11C16/26 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0407

Abstract: A data accessing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: reading a first physical programming unit by using a first read voltage to obtain first data; reading the first physical programming unit by using a second read voltage to obtain second data; inputting a first state parameter corresponding to the first data and a second state parameter corresponding to the second data into a numerical calculation engine, and determining a third reading voltage for reading the first physical programming unit by the numerical calculation engine.

公开(公告)号：US11809706B2

公开(公告)日：2023-11-07

申请号：US17349918

申请日：2021-06-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Siang Yang ,  Yu-Cheng Hsu ,  Tsai-Hao Kuo ,  Wei Lin ,  An-Cheng Liu

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0679

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes: reading first data from a first physical unit by using a first read voltage level according to first management information among multiple candidate management information; decoding the first data and recording first error bit information of the first data; and adjusting sorting information related to the candidate management information according to the first error bit information. The sorting information reflects a usage order of the candidate management information in a decoding operation.

公开(公告)号：US11561719B2

公开(公告)日：2023-01-24

申请号：US17242240

申请日：2021-04-27

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Siang Yang ,  Wei Lin ,  An-Cheng Liu ,  Yu-Heng Liu ,  Chun-Hsi Lai ,  Ting-Chien Zhan

IPC: G06F3/06

Abstract: A flash memory control method, a flash memory storage device and a flash memory controller are provided. The method includes the following. A flash memory module is instructed to perform a data merge operation to copy first data in a first physical unit into at least one second physical unit. After the first data is copied and before the first physical unit is erased, another programming operation is performed on the first physical unit to change a data storage state of at least a part of memory cells in the first physical unit from a first state into a second state. After the first physical unit is programmed, an erase operation is performed on the first physical unit.

公开(公告)号：US10923212B2

公开(公告)日：2021-02-16

申请号：US16251105

申请日：2019-01-18

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  An-Cheng Liu ,  Yu-Cheng Hsu ,  Yu-Siang Yang

IPC: G11C29/50 ,  G06F3/06 ,  G11C29/12 ,  G11C29/14 ,  G06F11/10 ,  G11C29/52

Abstract: A memory control method for a rewritable non-volatile memory module including a plurality of physical units is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first physical unit of a rewritable non-volatile memory module; decoding the first data by a decoding circuit; updating reliability information according to the decoded first data; reading second data from a second physical unit of the rewritable non-volatile memory module; and decoding the second data by the decoding circuit according to the updated reliability information.