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    Memory management method, memory storage device and memory control circuit unit
    1.
    发明授权
    Memory management method, memory storage device and memory control circuit unit 有权

    公开(公告)号：US11954329B2

    公开(公告)日：2024-04-09

    申请号：US17721358

    申请日：2022-04-15

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Chih-Kang Yeh

    IPC: G06F3/06

    CPC classification number: G06F3/0604 ,  G06F3/0652 ,  G06F3/0679

    Abstract: A memory management method configured for a rewritable non-volatile memory module, a memory storage device, and a memory control circuit unit are provided. The rewritable non-volatile memory module includes a plurality of dies, wherein each of the dies includes a plurality of planes, each of the planes includes a plurality of physical erasing units, and a sum of a number of the planes included in the rewritable non-volatile memory module is a first number. The method includes: grouping the plurality of physical erasing units into a plurality of management units. Each of the plurality of physical erasing units included in each of the management units belongs to a different plane, and each of the management units has a second number of the physical erasing units, wherein the second number is less than the first number.

    Data storing method, memory control circuit unit and memory storage device
    2.
    发明授权
    Data storing method, memory control circuit unit and memory storage device 有权

    公开(公告)号：US10824368B2

    公开(公告)日：2020-11-03

    申请号：US15729666

    申请日：2017-10-10

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Chih-Kang Yeh

    IPC: G06F3/06 ,  G06F13/16

    Abstract: A data storing method, a memory control circuit unit and a memory storage device are provided. The method includes: receiving a first write command from a host system; determining whether to write a first data corresponding to the first write command by using a first mode or write the first data by using a second mode according to an available buffer memory state; writing the first data into a first physical erasing unit among a plurality of physical erasing units by using the first mode when the first data is determined to be written by using the first mode; and writing the first data into a second physical erasing unit among the physical erasing units by using the second mode when the first data is determined to be written by using the second mode.

    DATA MERGE METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT
    3.
    发明申请
    DATA MERGE METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROL CIRCUIT UNIT 审中-公开

    公开(公告)号：US20200050399A1

    公开(公告)日：2020-02-13

    申请号：US16141990

    申请日：2018-09-26

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Chih-Kang Yeh

    IPC: G06F3/06

    Abstract: An exemplary embodiment of the disclosure provides a data merge method for a memory storage device. The method comprises: performing a data merge operation to store valid data collected from a source node comprising at least one first physical unit to a recycling node comprising a second physical unit. The data merge operation comprises: reading a first data from the at least one first physical unit by a first reading operation; performing a first stage programming operation on the second physical unit according to the first data; reading the first data from the at least one first physical unit again by a second reading operation after the first stage programming operation is performed; and performing a second stage programming operation on the second physical unit according to the first data read by the second reading operation.

    MEMORY MANAGEMENT METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE
    6.
    发明申请
    MEMORY MANAGEMENT METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE 有权

    公开(公告)号：US20180129414A1

    公开(公告)日：2018-05-10

    申请号：US15390547

    申请日：2016-12-26

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Chih-Kang Yeh

    IPC: G06F3/06 ,  G06F12/02

    CPC classification number: G06F3/061 ,  G06F3/0655 ,  G06F3/0679 ,  G06F12/0246 ,  G06F2212/7201

    Abstract: A memory management method, a memory control circuit unit and a memory storage device are provided, wherein the memory storage device includes a rewritable non-volatile memory module and a buffer memory. The method includes: loading at least one first address information of at least one first logical-physical mapping table from the rewritable non-volatile memory module to a first buffer area when the memory storage device is operated in a first mode, wherein the first address information has a first data quantity; and loading at least one second address information of at least one second logical-physical mapping table from the rewritable non-volatile memory module to the first buffer area when the memory storage device is operated in a second mode, wherein the second address information has a second data quantity, and the first data quantity is less than the second data quantity.

    Valid data merging method, memory controller and memory storage apparatus
    7.
    发明授权
    Valid data merging method, memory controller and memory storage apparatus 有权

    公开(公告)号：US09880742B2

    公开(公告)日：2018-01-30

    申请号：US14872154

    申请日：2015-10-01

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Chih-Kang Yeh

    IPC: G06F12/00 ,  G06F3/06 ,  G06F12/02 ,  G06F12/1009

    CPC classification number: G06F3/0608 ,  G06F3/0652 ,  G06F3/0679 ,  G06F12/0246 ,  G06F12/1009 ,  G06F2212/1044 ,  G06F2212/2022 ,  G06F2212/7201

    Abstract: A valid data merging method, a memory controller and a memory storage apparatus are provided. The method includes: selecting a first physical erasing unit, and loading a first logical address-physical address mapping table according to a physical address-logical address mapping table. The method also includes: updating the first logical address-physical address mapping table according to the physical address-logical address mapping table, and identifying valid data in the first physical erasing unit according to the physical address-logical address mapping table and the first logical address-physical address mapping table. The method further includes: storing the first logical address-physical address mapping table, copying the valid data to a second physical erasing unit, and performing an erasing operation for the first physical erasing unit.

    Data storing method for preventing data losing during flush operation, memory control circuit unit and memory storage apparatus
    8.
    发明授权
    Data storing method for preventing data losing during flush operation, memory control circuit unit and memory storage apparatus 有权

    公开(公告)号：US09778862B2

    公开(公告)日：2017-10-03

    申请号：US14195871

    申请日：2014-03-04

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Chih-Kang Yeh

    IPC: G06F3/06 ,  G06F12/02 ,  G11C11/56

    CPC classification number: G06F3/0619 ,  G06F3/0656 ,  G06F3/0679 ,  G06F12/02 ,  G06F12/0246 ,  G11C11/5628

    Abstract: A data storing method for storing data in a rewritable non-volatile memory module is provided. The method includes temporarily storing first data into a buffer memory; and starting a flush operation to write the first data from the buffer memory into a first physical programming unit. The method further includes determining whether the first physical programming unit is a lower physical programming unit; and if yes, writing second data into a second physical programming unit, wherein the second physical programming unit belongs to an upper physical programming unit, and the second physical programming unit and the first physical programming unit are formed by the same memory cells disposed on the same word line. Accordingly, the method can effectively prevent the data written during the flush operation from losing due to the programming fail occurred on other physical programming units.

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