公开(公告)号：US11561719B2

公开(公告)日：2023-01-24

申请号：US17242240

申请日：2021-04-27

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Siang Yang ,  Wei Lin ,  An-Cheng Liu ,  Yu-Heng Liu ,  Chun-Hsi Lai ,  Ting-Chien Zhan

IPC: G06F3/06

Abstract: A flash memory control method, a flash memory storage device and a flash memory controller are provided. The method includes the following. A flash memory module is instructed to perform a data merge operation to copy first data in a first physical unit into at least one second physical unit. After the first data is copied and before the first physical unit is erased, another programming operation is performed on the first physical unit to change a data storage state of at least a part of memory cells in the first physical unit from a first state into a second state. After the first physical unit is programmed, an erase operation is performed on the first physical unit.

公开(公告)号：US20220334723A1

公开(公告)日：2022-10-20

申请号：US17242240

申请日：2021-04-27

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Siang Yang ,  Wei Lin ,  An-Cheng Liu ,  Yu-Heng Liu ,  Chun-Hsi Lai ,  Ting-Chien Zhan

IPC: G06F3/06

Abstract: A flash memory control method, a flash memory storage device and a flash memory controller are provided. The method includes the following. A flash memory module is instructed to perform a data merge operation to copy first data in a first physical unit into at least one second physical unit. After the first data is copied and before the first physical unit is erased, another programming operation is performed on the first physical unit to change a data storage state of at least a part of memory cells in the first physical unit from a first state into a second state. After the first physical unit is programmed, an erase operation is performed on the first physical unit.

公开(公告)号：US11615848B2

公开(公告)日：2023-03-28

申请号：US17214958

申请日：2021-03-29

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Siang Yang ,  Wei Lin ,  An-Cheng Liu ,  Yu-Heng Liu ,  Chun-Hsi Lai ,  Ting-Chien Zhan

IPC: G11C16/00 ,  G11C16/10 ,  G06F3/06 ,  G11C16/04 ,  G11C16/14 ,  G11C16/08 ,  G11C11/56

Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: programming multiple first memory cells in a first physical erasing unit in a rewritable non-volatile memory module; and applying an electronic pulse to at least one word line in the rewritable non-volatile memory module. The at least one word line is coupled to multiple second memory cells in the first physical erasing unit. The second memory cells include the first memory cells. The electronic pulse is not configured to read, program, or erase the second memory cells.

公开(公告)号：US20220293185A1

公开(公告)日：2022-09-15

申请号：US17214958

申请日：2021-03-29

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Siang Yang ,  Wei Lin ,  An-Cheng Liu ,  Yu-Heng Liu ,  Chun-Hsi Lai ,  Ting-Chien Zhan

IPC: G11C16/10 ,  G06F3/06 ,  G11C16/04 ,  G11C16/14 ,  G11C16/08

Abstract: A memory control method, a memory storage device, and a memory control circuit unit are provided. The memory control method includes: programming multiple first memory cells in a first physical erasing unit in a rewritable non-volatile memory module; and applying an electronic pulse to at least one word line in the rewritable non-volatile memory module. The at least one word line is coupled to multiple second memory cells in the first physical erasing unit. The second memory cells include the first memory cells. The electronic pulse is not configured to read, program, or erase the second memory cells.