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    Valid data merging method, memory controller and memory storage apparatus
    1.
    发明授权
    Valid data merging method, memory controller and memory storage apparatus 有权

    公开(公告)号：US10289334B2

    公开(公告)日：2019-05-14

    申请号：US14986733

    申请日：2016-01-04

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Horng-Sheng Yan

    IPC: G06F3/06

    Abstract: A valid data merging method, a memory controller and a memory storage apparatus are provided. The method includes: grouping physical erasing units in a data area to at least a first group and a second group; selecting a first physical erasing unit from the second group; and copying valid data of the first physical erasing unit to a second physical erasing unit. A trim table recording special type data of the physical erasing units of the first group is not stored in a non-volatile rewriteable memory module, and a trim table recording special type data of the physical erasing units of the second group is stored in the non-volatile rewriteable memory module. The valid data does not include the special type data of the first physical erasing unit.

    Data protecting method, memory control circuit unit and memory storage device
    2.
    发明授权
    Data protecting method, memory control circuit unit and memory storage device 有权

    公开(公告)号：US09720609B1

    公开(公告)日：2017-08-01

    申请号：US15147914

    申请日：2016-05-06

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Horng-Sheng Yan ,  Kok-Yong Tan

    IPC: G06F12/00 ,  G06F3/06

    CPC classification number: G06F3/0619 ,  G06F3/0655 ,  G06F3/0688 ,  G06F11/1068 ,  G11C29/52 ,  G11C29/76

    Abstract: A data protecting method for a rewritable non-volatile memory module is provided. The method includes assigning a plurality of physical pages into a plurality of encoding groups to group a first physical page to a first encoding group and group a second physical page to a second encoding group, where each of the physical pages stores user data and a parity code corresponding to the user data, the first physical page is composed of memory cells of a first word line, and the second physical page is composed of memory cells of a second word line adjacent to the first word line. The method also includes respectively encoding the user data in the physical pages of the encoding groups for generating a plurality of group parity codes respectively corresponding to the encoding groups.

    Memory management method, memory control circuit unit and memory storage device
    3.
    发明授权
    Memory management method, memory control circuit unit and memory storage device 有权

    公开(公告)号：US10338854B2

    公开(公告)日：2019-07-02

    申请号：US14846830

    申请日：2015-09-07

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Kok-Yong Tan ,  Horng-Sheng Yan

    IPC: G06F12/02 ,  G06F3/06

    Abstract: A memory management method, a memory control circuit unit and a memory storage device are provided. In an exemplary embodiment, the memory management method includes: receiving a first write command and first write data and obtaining a first number; programming the first write data and moving first storage data stored in a plurality of first physical programming units, where a total number of the first physical programming units conforms to the first number; receiving a second write command and second write data and obtaining a second number; programming the second write data and moving second storage data stored in a plurality of second physical programming units, where a total number of the second physical programming units conforms to the second number; and erasing at least one physical erasing unit. Accordingly, waste of system resource in the data merging procedure may be reduced.

    MEMORY MANAGEMENT METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE
    4.
    发明申请
    MEMORY MANAGEMENT METHOD, MEMORY CONTROL CIRCUIT UNIT AND MEMORY STORAGE DEVICE 审中-公开
    存储器管理方法，存储器控制电路单元和存储器存储器件

    公开(公告)号：US20170024136A1

    公开(公告)日：2017-01-26

    申请号：US14846830

    申请日：2015-09-07

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Kok-Yong Tan ,  Horng-Sheng Yan

    IPC: G06F3/06

    CPC classification number: G06F3/0679 ,  G06F3/0616 ,  G06F3/0652 ,  G06F3/0659 ,  G06F12/0246 ,  G06F12/0253 ,  G06F2212/7205

    Abstract: A memory management method, a memory control circuit unit and a memory storage device are provided. In an exemplary embodiment, the memory management method includes: receiving a first write command and first write data and obtaining a first number; programming the first write data and moving first storage data stored in a plurality of first physical programming units, where a total number of the first physical programming units conforms to the first number; receiving a second write command and second write data and obtaining a second number; programming the second write data and moving second storage data stored in a plurality of second physical programming units, where a total number of the second physical programming units conforms to the second number; and erasing at least one physical erasing unit. Accordingly, waste of system resource in the data merging procedure may be reduced.

    Abstract translation: 提供存储器管理方法，存储器控制电路单元和存储器存储装置。 在一个示例性实施例中，存储器管理方法包括：接收第一写入命令和首先写入数据并获得第一个数字; 编程所述第一写入数据和移动存储在多个第一物理编程单元中的第一存储数据，其中所述第一物理编程单元的总数符合所述第一数量; 接收第二写入命令和第二写入数据并获得第二个数字; 编程所述第二写数据和移动存储在多个第二物理编程单元中的第二存储数据，其中所述第二物理编程单元的总数符合所述第二数目; 并擦除至少一个物理擦除单元。 因此，可以减少数据合并过程中的系统资源浪费。

    Error handling method, memory storage device and memory controlling circuit unit
    6.
    发明授权
    Error handling method, memory storage device and memory controlling circuit unit 有权
    错误处理方法，存储器存储器和存储器控制电路单元

    公开(公告)号：US09229798B2

    公开(公告)日：2016-01-05

    申请号：US14248346

    申请日：2014-04-09

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Horng-Sheng Yan

    IPC: G06F11/00 ,  G06F11/07

    CPC classification number: G06F11/0727 ,  G06F11/073 ,  G06F11/0742 ,  G06F11/076

    Abstract: An error handling method, a memory storage device and a memory controlling circuit unit are provided. The method includes obtaining a finished event corresponding to a channel; determining whether the finished event is a failed event, if the finished event is the failed event; stopping an operation of the channel and performing a first update operation on a counting value corresponding to the channel; and if the finished event is not the failed event, keeping the counting value corresponding to the channel unchanged and processing the finished event. The step of the processing the finished event includes performing a second update operation on the counting value corresponding to the channel if the finished event is the failed event, and recovering the operation of the channel if the counting value matches a threshold criterion. Accordingly, it can improve the accessing performance.

    Abstract translation: 提供错误处理方法，存储器存储装置和存储器控制电路单元。 该方法包括获得与频道相对应的完成事件; 确定完成的事件是否是失败的事件，如果完成的事件是失败的事件; 停止对信道的操作，并对与该信道相对应的计数值执行第一更新操作; 并且如果完成的事件不是故障事件，则保持对应于通道的计数值不变并处理完成的事件。 处理完成的事件的步骤包括如果完成的事件是故障事件，则对与通道相对应的计数值执行第二更新操作，如果计数值与阈值标准匹配，则恢复通道的操作。 因此，可以提高访问性能。

    Memory management method, memory control circuit unit and memory storage device
    7.
    发明授权
    Memory management method, memory control circuit unit and memory storage device 有权

    公开(公告)号：US10101914B2

    公开(公告)日：2018-10-16

    申请号：US15093755

    申请日：2016-04-08

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Kok-Yong Tan ,  Horng-Sheng Yan

    IPC: G06F12/02 ,  G06F3/06

    Abstract: A memory management method for a rewritable non-volatile memory module is provided. The memory management method includes receiving an adjust command from a host system, wherein the adjust command is configured to indicate that data stored in at least one logical unit of a plurality of logical units is invalid; updating a logical address status table according to the adjust command, wherein the logical address status table reflects a data status of the data stored in each of the logical units, wherein the data status includes a first state or a second state; and updating a physical address status table according to the logical address status table and the physical address status table if a predetermined condition is met, wherein the physical address status table reflects a data status of data stored in each of a plurality of physical programming units.

    ERROR HANDLING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT
    9.
    发明申请
    ERROR HANDLING METHOD, MEMORY STORAGE DEVICE AND MEMORY CONTROLLING CIRCUIT UNIT 有权
    错误处理方法，存储器存储器和存储器控制电路单元

    公开(公告)号：US20150193291A1

    公开(公告)日：2015-07-09

    申请号：US14248346

    申请日：2014-04-09

    Applicant: PHISON ELECTRONICS CORP.

    Inventor： Horng-Sheng Yan

    IPC: G06F11/07

    CPC classification number: G06F11/0727 ,  G06F11/073 ,  G06F11/0742 ,  G06F11/076

    Abstract: An error handling method, a memory storage device and a memory controlling circuit unit are provided. The method includes obtaining a finished event corresponding to a channel; determining whether the finished event is a failed event, if the finished event is the failed event; stopping an operation of the channel and performing a first update operation on a counting value corresponding to the channel; and if the finished event is not the failed event, keeping the counting value corresponding to the channel unchanged and processing the finished event. The step of the processing the finished event includes performing a second update operation on the counting value corresponding to the channel if the finished event is the failed event, and recovering the operation of the channel if the counting value matches a threshold criterion. Accordingly, it can improve the accessing performance.

    Abstract translation: 提供错误处理方法，存储器存储装置和存储器控制电路单元。 该方法包括获得与频道相对应的完成事件; 确定完成的事件是否是失败的事件，如果完成的事件是失败的事件; 停止对信道的操作，并对与该信道相对应的计数值执行第一更新操作; 并且如果完成的事件不是故障事件，则保持对应于通道的计数值不变并处理完成的事件。 处理完成的事件的步骤包括如果完成的事件是故障事件，则对与通道相对应的计数值执行第二更新操作，如果计数值与阈值标准匹配，则恢复通道的操作。 因此，可以提高访问性能。

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