公开(公告)号：US20250036308A1

公开(公告)日：2025-01-30

申请号：US18469561

申请日：2023-09-19

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F3/06

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes establishing a connection between the memory storage device and a host system; receiving a first request from the host system via the connection; detecting a status of the memory storage device in a time range according to the first request; and determining whether to use a memory in the host system according to the status.

公开(公告)号：US20230297464A1

公开(公告)日：2023-09-21

申请号：US17715050

申请日：2022-04-07

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F11/07 ,  G06F1/30 ,  G06F3/06

CPC classification number: G06F11/0793 ,  G06F1/30 ,  G06F11/073 ,  G06F3/0625 ,  G06F3/065 ,  G06F3/0689 ,  G06F3/0619

Abstract: An abnormal power loss recovery method, a memory control circuit unit, and a memory storage device are provided. The method is configured for a memory storage device including a rewritable non-volatile memory module having a plurality of super-physical units. The super-physical units include at least two physical erasing units, and each of the physical erasing units belongs to a different operation unit and includes a plurality of physical programming units. The method includes: reading data stored in a first super-physical unit without a corresponding RAID ECC code when a memory storage device is powered on again and detected as an abnormal power loss to obtain first data, and the first super-physical unit is a last super-physical unit to which data is written before the abnormal power loss occurs; and copying the first data to a second super-physical unit.

公开(公告)号：US20190324904A1

公开(公告)日：2019-10-24

申请号：US16004443

申请日：2018-06-11

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F12/0804 ,  G06F12/10

Abstract: A trim command recording method, a memory control circuit unit and a memory storage device are provided. The method includes: receiving a write command from a host system; writing a data corresponding to the write command to a first physical programming unit of a first physical erasing unit in the plurality of physical erasing units; and when receiving a trim command from the host system, writing a trim command record corresponding to the trim command into a second physical programming unit of the first physical erasing unit.

公开(公告)号：US10338854B2

公开(公告)日：2019-07-02

申请号：US14846830

申请日：2015-09-07

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan ,  Horng-Sheng Yan

IPC: G06F12/02 ,  G06F3/06

Abstract: A memory management method, a memory control circuit unit and a memory storage device are provided. In an exemplary embodiment, the memory management method includes: receiving a first write command and first write data and obtaining a first number; programming the first write data and moving first storage data stored in a plurality of first physical programming units, where a total number of the first physical programming units conforms to the first number; receiving a second write command and second write data and obtaining a second number; programming the second write data and moving second storage data stored in a plurality of second physical programming units, where a total number of the second physical programming units conforms to the second number; and erasing at least one physical erasing unit. Accordingly, waste of system resource in the data merging procedure may be reduced.

公开(公告)号：US20170255389A1

公开(公告)日：2017-09-07

申请号：US15140494

申请日：2016-04-28

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F3/06

CPC classification number: G06F3/0605 ,  G06F3/0611 ,  G06F3/0616 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0656 ,  G06F3/0659 ,  G06F3/0679 ,  G06F12/0238 ,  G06F12/0246

Abstract: A data transmitting method for a memory storage device is provided. The method includes: detecting a temperature of the memory storage device; and determining whether the temperature of the memory storage device is greater than a temperature threshold. If the temperature is greater than the temperature threshold, first data is written into a rewritable non-volatile memory module within a first delay time according to a delay count corresponding to a unit temperature.

公开(公告)号：US20170024136A1

公开(公告)日：2017-01-26

申请号：US14846830

申请日：2015-09-07

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan ,  Horng-Sheng Yan

IPC: G06F3/06

CPC classification number: G06F3/0679 ,  G06F3/0616 ,  G06F3/0652 ,  G06F3/0659 ,  G06F12/0246 ,  G06F12/0253 ,  G06F2212/7205

Abstract: A memory management method, a memory control circuit unit and a memory storage device are provided. In an exemplary embodiment, the memory management method includes: receiving a first write command and first write data and obtaining a first number; programming the first write data and moving first storage data stored in a plurality of first physical programming units, where a total number of the first physical programming units conforms to the first number; receiving a second write command and second write data and obtaining a second number; programming the second write data and moving second storage data stored in a plurality of second physical programming units, where a total number of the second physical programming units conforms to the second number; and erasing at least one physical erasing unit. Accordingly, waste of system resource in the data merging procedure may be reduced.

Abstract translation: 提供存储器管理方法，存储器控制电路单元和存储器存储装置。 在一个示例性实施例中，存储器管理方法包括：接收第一写入命令和首先写入数据并获得第一个数字; 编程所述第一写入数据和移动存储在多个第一物理编程单元中的第一存储数据，其中所述第一物理编程单元的总数符合所述第一数量; 接收第二写入命令和第二写入数据并获得第二个数字; 编程所述第二写数据和移动存储在多个第二物理编程单元中的第二存储数据，其中所述第二物理编程单元的总数符合所述第二数目; 并擦除至少一个物理擦除单元。 因此，可以减少数据合并过程中的系统资源浪费。

公开(公告)号：US12216933B1

公开(公告)日：2025-02-04

申请号：US18469561

申请日：2023-09-19

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F3/06

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes establishing a connection between the memory storage device and a host system; receiving a first request from the host system via the connection; detecting a status of the memory storage device in a time range according to the first request; and determining whether to use a memory in the host system according to the status.

公开(公告)号：US20250021233A1

公开(公告)日：2025-01-16

申请号：US18363758

申请日：2023-08-02

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F3/06

Abstract: A memory management method, a memory storage device and a memory control circuit unit are disclosed. The method includes: in an initialization operation, setting a first physical unit to be operated in a first operation mode, and in the first operation mode, the first physical unit is programmed based on a first programming mode; receiving a plurality of commands, and the commands includes a first command and a second command, the first command instructs to store first data to a first logical unit, and the second command instructs to mark second data stored in a second logical unit as invalid data; and in response to that a target condition is satisfied, setting the first physical unit to be operated in a second operation mode, and in the second operation mode, the first physical unit is programmable based on a second programming mode.

公开(公告)号：US11609822B2

公开(公告)日：2023-03-21

申请号：US17337428

申请日：2021-06-03

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F11/07 ,  G06F11/14 ,  G06F1/30 ,  G06F12/02 ,  G06F11/30

Abstract: A data storing method, a memory control circuit unit and a memory storage device are provided. The method includes the following. When the memory storage device is powered-on, it is determined whether a power loss state of the memory storage device matches an unexpected power loss state according to a power-off instruction. Data is written into a plurality of physical programming units using a single-page programming mode and not using a multi-page programming mode when it is determined that the power loss state matches the unexpected power loss state.

公开(公告)号：US20210255950A1

公开(公告)日：2021-08-19

申请号：US16835268

申请日：2020-03-30

Applicant: PHISON ELECTRONICS CORP.

Inventor： Kok-Yong Tan

IPC: G06F12/02 ,  G06F12/0882 ,  G06F12/06 ,  G06F9/30 ,  G06F11/30 ,  G11C16/14

Abstract: A data arrangement method, a memory storage device and a memory control circuit unit are provided. The data arrangement method includes: receiving a command from a host, and the command includes a data range; calculating a data disarranged degree according to a logical estimated value of a plurality of logical block addresses of the data range and a physical estimated value of a plurality of physical erasing units mapped to the plurality of logical block addresses of the data range; and determining whether to perform a data arrangement operation according to the data disarranged degree and a threshold to move data in the plurality of physical erasing units according to the plurality of logical block addresses.