公开(公告)号：US11238902B2

公开(公告)日：2022-02-01

申请号：US16858748

申请日：2020-04-27

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Chien Huang ,  Chien Ho Liao

IPC: G11C5/02 ,  G11C11/406 ,  G11C5/06

Abstract: A circuit layout structure and a memory storage device are disclosed. The circuit layout structure includes a plurality of first volatile memory modules, a plurality of second volatile memory modules, a first data line, a second data line, a first clock enable signal line and a second clock enable signal line. The first data line is configured to access the first volatile memory modules in parallel by a first sequential bit group. The second data line is configured to access the second volatile memory modules in parallel by a second sequential bit group. The first clock enable signal line and the second clock enable signal line are configured to control the first volatile memory modules and the second volatile memory modules to enter a self-refresh mode respectively.

公开(公告)号：US20210027824A1

公开(公告)日：2021-01-28

申请号：US16568193

申请日：2019-09-11

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Chien Huang

IPC: G11C11/4063 ,  G11C5/06 ,  G11C29/44 ,  G11C7/10

Abstract: A memory interface circuit, a memory storage device and a configuration status checking method are provided. The memory interface circuit is configured to connect a plurality of volatile memory modules and a memory controller. The volatile memory modules include a first volatile memory module and a second volatile memory module. The memory interface circuit includes a first interface circuit and a second interface circuit. The first interface circuit is configured to receive a first signal from the first volatile memory module and transmit a second signal to the second interface circuit through an internal path of the memory interface circuit. The second interface circuit is configured to transmit a third signal to the second volatile memory module according to the second signal to evaluate a configuration status of the memory interface circuit by the third signal.

公开(公告)号：US12008242B2

公开(公告)日：2024-06-11

申请号：US17983407

申请日：2022-11-09

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yi-Chung Chen ,  Ming-Chien Huang

IPC: G06F3/06 ,  G11C11/4076

CPC classification number: G06F3/0614 ,  G06F3/0629 ,  G06F3/0673 ,  G11C11/4076

Abstract: A signal calibration method, a memory storage device, and a memory control circuit unit are provided. The signal calibration method includes: generating a clock signal and a data strobe signal according to an internal clock signal; respectively transmitting the clock signal and the data strobe signal to a target volatile memory module among multiple volatile memory modules through a first signal path and a second signal path; obtaining a shift value between the data strobe signal and the clock signal at the target volatile memory module; and storing an initial delay setting of the data strobe signal according to delay information of the data strobe signal in response to the shift value being greater than a threshold value.

公开(公告)号：US20170365328A1

公开(公告)日：2017-12-21

申请号：US15591114

申请日：2017-05-10

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Chien Huang ,  Chia-Lung Ma ,  Tzu-Chia Huang

IPC: G11C11/4093 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4099

CPC classification number: G11C11/4093 ,  G06F13/16 ,  G11C5/147 ,  G11C7/1084 ,  G11C11/005 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4099 ,  G11C2207/10

Abstract: A memory control circuit unit, a memory storage device and a signal receiving method. In one exemplary embodiment, a memory interface circuit of the memory control circuit unit receives a first signal from a volatile memory and adjusts a voltage value of the first signal to a voltage range in response to an internal impedance of the memory interface circuit, where a central value of the voltage range is not equal to a default voltage value, and the default voltage value is one half a sum of a voltage value of a supply voltage of the memory interface circuit and a voltage value of a reference ground voltage. In addition, the memory interface circuit further generates an input signal according to a voltage correspondence between the first signal and an internal reference voltage.

公开(公告)号：US09685221B1

公开(公告)日：2017-06-20

申请号：US15241094

申请日：2016-08-19

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Chien Huang

IPC: G11C16/30 ,  G11C11/4074 ,  G11C11/4076

CPC classification number: G11C11/4074 ,  G06F13/16 ,  G06F13/1668 ,  G11C5/147 ,  G11C11/4093 ,  G11C16/30

Abstract: A memory control circuit unit, a memory storage device and a reference voltage generation method are provided. The method comprises: detecting a first impedance characteristic of a memory controller via a first connection interface of a memory interface and detecting a second impedance characteristic of a volatile memory via a second connection interface of the memory interface; generating an internal reference voltage according to a detection result; and resolving data signal received by the memory interface according to the internal reference voltage. Therefore, an influence on the internal reference voltage owing to the manufacture deviation of impedance element of the memory controller and/or the volatile memory can be reduced.

公开(公告)号：US20240111448A1

公开(公告)日：2024-04-04

申请号：US17978234

申请日：2022-11-01

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Chien Huang

IPC: G06F3/06 ,  G06F1/04

CPC classification number: G06F3/0655 ,  G06F1/04 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory control circuit unit, a memory storage device, and a clock signal control method are provided. The method includes: executing an access operation on a volatile memory module through a memory interface circuit; setting a duty cycle of a first clock signal according to a type of the access operation; and transmitting the first clock signal to the volatile memory module to execute the access operation.

公开(公告)号：US20240111430A1

公开(公告)日：2024-04-04

申请号：US17983407

申请日：2022-11-09

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yi-Chung Chen ,  Ming-Chien Huang

IPC: G06F3/06 ,  G11C11/4076

CPC classification number: G06F3/0614 ,  G06F3/0629 ,  G06F3/0673 ,  G11C11/4076

Abstract: A signal calibration method, a memory storage device, and a memory control circuit unit are provided. The signal calibration method includes: generating a clock signal and a data strobe signal according to an internal clock signal; respectively transmitting the clock signal and the data strobe signal to a target volatile memory module among multiple volatile memory modules through a first signal path and a second signal path; obtaining a shift value between the data strobe signal and the clock signal at the target volatile memory module; and storing an initial delay setting of the data strobe signal according to delay information of the data strobe signal in response to the shift value being greater than a threshold value.

公开(公告)号：US20210295877A1

公开(公告)日：2021-09-23

申请号：US16858748

申请日：2020-04-27

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Chien Huang ,  Chien Ho Liao

IPC: G11C5/02 ,  G11C5/06 ,  G11C11/406

Abstract: A circuit layout structure and a memory storage device are disclosed. The circuit layout structure includes a plurality of first volatile memory modules, a plurality of second volatile memory modules, a first data line, a second data line, a first clock enable signal line and a second clock enable signal line. The first data line is configured to access the first volatile memory modules in parallel by a first sequential bit group. The second data line is configured to access the second volatile memory modules in parallel by a second sequential bit group. The first clock enable signal line and the second clock enable signal line are configured to control the first volatile memory modules and the second volatile memory modules to enter a self-refresh mode respectively.

公开(公告)号：US10304521B2

公开(公告)日：2019-05-28

申请号：US15955701

申请日：2018-04-18

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Chien Huang ,  Chia-Lung Ma ,  Tzu-Chia Huang

IPC: G11C5/14 ,  G11C11/4093 ,  G11C11/4099 ,  G11C11/4096 ,  G11C11/4074 ,  G06F13/16 ,  G11C7/10 ,  G11C11/00 ,  G06F12/00

Abstract: A memory control circuit unit, a memory storage device and a signal receiving method. In one exemplary embodiment, a memory interface circuit of the memory control circuit unit receives a first signal from a volatile memory and adjusts a voltage value of the first signal to a voltage range in response to an internal impedance of the memory interface circuit, where a central value of the voltage range is not equal to a default voltage value, and the default voltage value is one half a sum of a voltage value of a supply voltage of the memory interface circuit and a voltage value of a reference ground voltage. In addition, the memory interface circuit further generates an input signal according to a voltage correspondence between the first signal and an internal reference voltage.

公开(公告)号：US09990983B2

公开(公告)日：2018-06-05

申请号：US15591114

申请日：2017-05-10

Applicant: PHISON ELECTRONICS CORP.

Inventor： Ming-Chien Huang ,  Chia-Lung Ma ,  Tzu-Chia Huang

IPC: G11C16/30 ,  G11C11/4093 ,  G11C11/4074 ,  G11C11/4099 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G06F13/16 ,  G11C5/147 ,  G11C7/1084 ,  G11C11/005 ,  G11C11/4074 ,  G11C11/4096 ,  G11C11/4099 ,  G11C2207/10

Abstract: A memory control circuit unit, a memory storage device and a signal receiving method. In one exemplary embodiment, a memory interface circuit of the memory control circuit unit receives a first signal from a volatile memory and adjusts a voltage value of the first signal to a voltage range in response to an internal impedance of the memory interface circuit, where a central value of the voltage range is not equal to a default voltage value, and the default voltage value is one half a sum of a voltage value of a supply voltage of the memory interface circuit and a voltage value of a reference ground voltage. In addition, the memory interface circuit further generates an input signal according to a voltage correspondence between the first signal and an internal reference voltage.