公开(公告)号：US20190318791A1

公开(公告)日：2019-10-17

申请号：US16003114

申请日：2018-06-08

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  An-Cheng Liu ,  Szu-Wei Chen ,  Yu-Siang Yang

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G06F3/06

Abstract: A memory management method for a memory storage device including a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: programming first data into a plurality of first memory cells in the rewritable non-volatile memory module, such that the programmed first memory cells have a plurality of states; sending a first single-stage read command sequence which indicates to read the programmed first memory cells by using a first read voltage level; obtaining first count information corresponding to the first read voltage level according to a read result corresponding to the first single-stage read command sequence; and adjusting the first read voltage level according to the first count information and default count information corresponding to the first read voltage level.

公开(公告)号：US10424391B2

公开(公告)日：2019-09-24

申请号：US15811695

申请日：2017-11-14

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Szu-Wei Chen ,  Yu-Siang Yang

IPC: G11C29/00 ,  G11C29/52 ,  G11C16/10 ,  G06F12/02 ,  G06F11/10 ,  G11C16/30 ,  G11C16/08 ,  G11C16/26 ,  G11C11/56 ,  G11C16/04

Abstract: A decoding method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: when first data is read from a first upper physical programming unit of a first physical programming unit group by using a second voltage selected from a first read voltage group, and a first error bit count of the first data is not greater than a first error bit count threshold, recording the second voltage; when a second data is read from a first lower physical programming unit of a second physical programming unit group by using a fourth voltage selected from a second read voltage group, and a second error bit count of the second data is not greater than a second error bit count threshold, recording the fourth voltage; generating a lookup table according to the second voltage and the fourth voltage; and performing a decoding operation according to the lookup table.

公开(公告)号：US20180101317A1

公开(公告)日：2018-04-12

申请号：US15361008

申请日：2016-11-24

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Szu-Wei Chen

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G06F11/10 ,  G11C29/52

CPC classification number: G11C16/04 ,  G06F3/0619 ,  G06F11/1068 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3459 ,  H03M13/2957

Abstract: The memory programming method includes: applying a first programming parameter set to program first data stream into a first physical programming unit, and the first physical programming unit is composed of memory cells at intersections between a first bit line string of a physical erasing unit and a first word line layer of the physical erasing unit. The memory programming method further includes applying a second programming parameter set to program the first data stream into all of the memory cells of the first physical programming unit again after completely programming the first data stream into all of the memory cells of the first physical programming unit.

公开(公告)号：US20220027089A1

公开(公告)日：2022-01-27

申请号：US16994668

申请日：2020-08-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Shih-Jia Zeng ,  Yu-Siang Yang ,  Szu-Wei Chen ,  Wei Lin

IPC: G06F3/06 ,  G11C16/26

Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: determining a retry threshold value according to decoding history information which includes information related to at least one first decoding operation previously performed; and determining whether to enter a second decoding mode according to the retry threshold value after at least one second decoding operation performed based on a first decoding mode is failed. A decoding ability of the second decoding mode is higher than a decoding ability of the first decoding mode.

公开(公告)号：US10978163B2

公开(公告)日：2021-04-13

申请号：US16601517

申请日：2019-10-14

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  An-Cheng Liu ,  Szu-Wei Chen ,  Yu-Siang Yang

IPC: G11C16/26 ,  G11C11/56 ,  H03M7/42

Abstract: A voltage identifying method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a plurality of first memory cells according to a first read voltage group in a plurality of read voltage groups and performing a first decoding operation to generate first verification information; identifying a plurality of second read voltage groups in the plurality of read voltage groups corresponding to a first interval in a plurality of intervals according to the first interval in which the first verification information is located; and reading the plurality of first memory cells by using a third read voltage group in the plurality of second read voltage groups and performing the first decoding operation.

公开(公告)号：US20190163363A1

公开(公告)日：2019-05-30

申请号：US15867719

申请日：2018-01-11

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  An-Cheng Liu ,  Lih Yuarn Ou ,  Szu-Wei Chen

IPC: G06F3/06 ,  G11C16/26 ,  G06F11/10 ,  G11C29/52

CPC classification number: G06F3/061 ,  G06F3/0619 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/1068 ,  G06F11/1072 ,  G11C16/0483 ,  G11C16/26 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0407

Abstract: A data accessing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: reading a first physical programming unit by using a first read voltage to obtain first data; reading the first physical programming unit by using a second read voltage to obtain second data; inputting a first state parameter corresponding to the first data and a second state parameter corresponding to the second data into a numerical calculation engine, and determining a third reading voltage for reading the first physical programming unit by the numerical calculation engine.

公开(公告)号：US09812194B1

公开(公告)日：2017-11-07

申请号：US15481473

申请日：2017-04-07

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Szu-Wei Chen

IPC: G11C16/04 ,  G11C11/56 ,  G11C16/08

CPC classification number: G11C11/5642 ,  G11C16/0466 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/28 ,  G11C16/3418 ,  G11C16/3495

Abstract: A decoding method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: obtaining usage state information of first memory cells; reading second memory cells by a first read voltage level to obtain at least one first bit and reading the second memory cells by a second read voltage level to obtain at least one second bit according to the usage state information, wherein the first bit corresponds to a storage state of a first part of memory cells among the second memory cells, the second bit corresponds to a storage state of a second part of memory cell among the second memory cells, and the first read voltage level is different from the second read voltage level; and decoding third bits including the first bit and the second bit. Therefore, a decoding efficiency can be improved.

公开(公告)号：US20250123773A1

公开(公告)日：2025-04-17

申请号：US18504107

申请日：2023-11-07

Applicant: PHISON ELECTRONICS CORP.

Inventor： Jian Ping Syu ,  Wei Lin ,  Szu-Wei Chen ,  An-Cin Li

IPC: G06F3/06

Abstract: A memory operation method, a memory storage device, and a memory control circuit unit are disclosed. The memory operation includes following steps. First data is received from a host system. The first data is stored into a first physical unit which is mapped to a first logical unit. In a first operation mode, a target calculation is performed based on the first data and second data stored in a second physical unit to obtain third data, and the third data is different from the first data. The third data is stored into a third physical unit which is also mapped to the first logical unit. The third data is transmitted to the host system.

公开(公告)号：US10776053B2

公开(公告)日：2020-09-15

申请号：US16258693

申请日：2019-01-28

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Szu-Wei Chen ,  Yu-Siang Yang

IPC: G06F3/06 ,  G11C7/10 ,  G06F12/02 ,  G06F13/16

Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first memory cell of the rewritable non-volatile memory module by a first read voltage level; decoding the first data by a decoding circuit; reading second data from the first memory cell by a second read voltage level; obtaining reliability information according to a first data status of the first data and a second data status of the second data, and the first data status and the second data status reflect that a first bit value of the first data is different from a second bit value of the second data; and decoding the second data by the decoding circuit according to the reliability information.

公开(公告)号：US10445002B2

公开(公告)日：2019-10-15

申请号：US15867719

申请日：2018-01-11

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  An-Cheng Liu ,  Lih Yuarn Ou ,  Szu-Wei Chen

IPC: G06F3/06 ,  G11C16/26 ,  G06F11/10 ,  G11C16/04 ,  G11C29/02 ,  G11C29/52 ,  G11C29/04

Abstract: A data accessing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: reading a first physical programming unit by using a first read voltage to obtain first data; reading the first physical programming unit by using a second read voltage to obtain second data; inputting a first state parameter corresponding to the first data and a second state parameter corresponding to the second data into a numerical calculation engine, and determining a third reading voltage for reading the first physical programming unit by the numerical calculation engine.