公开(公告)号：US20240304259A1

公开(公告)日：2024-09-12

申请号：US18298335

申请日：2023-04-10

Applicant: PHISON ELECTRONICS CORP.

Inventor： Po-Cheng Su ,  Po-Hao Chen ,  Yu-Cheng Hsu ,  Wei Lin

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/34

CPC classification number: G11C16/26 ,  G11C16/08 ,  G11C16/3404

Abstract: A voltage prediction method, a memory storage device and a memory control circuit unit are disclosed. The method includes: reading a plurality of memory cells in a rewritable non-volatile memory module by using a first read voltage level to obtain count information, and the first read voltage level is configured to distinguish a first state and a second state adjacent to each other in a threshold voltage distribution of the memory cells, and the count information reflects a total number of first memory cells meeting a target condition among the memory cells; and predicting a second read voltage level according to the count information, and the second read voltage level is configured to distinguish a third state and a fourth state adjacent to each other in the threshold voltage distribution.

公开(公告)号：US11809706B2

公开(公告)日：2023-11-07

申请号：US17349918

申请日：2021-06-17

Applicant: PHISON ELECTRONICS CORP.

Inventor： Yu-Siang Yang ,  Yu-Cheng Hsu ,  Tsai-Hao Kuo ,  Wei Lin ,  An-Cheng Liu

IPC: G06F3/06

CPC classification number: G06F3/0604 ,  G06F3/0619 ,  G06F3/0655 ,  G06F3/0679

Abstract: A memory management method, a memory storage device, and a memory control circuit unit are provided. The method includes: reading first data from a first physical unit by using a first read voltage level according to first management information among multiple candidate management information; decoding the first data and recording first error bit information of the first data; and adjusting sorting information related to the candidate management information according to the first error bit information. The sorting information reflects a usage order of the candidate management information in a decoding operation.

公开(公告)号：US20210397347A1

公开(公告)日：2021-12-23

申请号：US16921874

申请日：2020-07-06

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Hsiao-Yi Lin ,  Yu-Siang Yang

IPC: G06F3/06

Abstract: A data protection method, a memory storage device and a memory control circuit unit are provided. The method includes: setting a plurality of disk array tags corresponding to a plurality of word lines and a plurality of memory planes, and the plurality of disk array tags corresponding to one of the word lines connected to one of the memory planes are at least partially identical to the plurality of disk array tags corresponding to another one of the word lines connected to another one of the memory planes; receiving a write command and data corresponding to the write command from a host system; and sequentially writing the data into the plurality of word lines and the plurality of memory planes corresponding to the plurality of disk array tags.

公开(公告)号：US10923212B2

公开(公告)日：2021-02-16

申请号：US16251105

申请日：2019-01-18

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  An-Cheng Liu ,  Yu-Cheng Hsu ,  Yu-Siang Yang

IPC: G11C29/50 ,  G06F3/06 ,  G11C29/12 ,  G11C29/14 ,  G06F11/10 ,  G11C29/52

Abstract: A memory control method for a rewritable non-volatile memory module including a plurality of physical units is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first physical unit of a rewritable non-volatile memory module; decoding the first data by a decoding circuit; updating reliability information according to the decoded first data; reading second data from a second physical unit of the rewritable non-volatile memory module; and decoding the second data by the decoding circuit according to the updated reliability information.

公开(公告)号：US20200379676A1

公开(公告)日：2020-12-03

申请号：US16452540

申请日：2019-06-26

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu

IPC: G06F3/06

Abstract: A data writing method, a memory controlling circuit unit and a memory storage device are provided. The method includes: receiving a plurality of data; writing the plurality of data into a first physical erasing unit by using a multi-page programming mode; and writing at least one first data of the plurality of data into a second physical erasing unit by using a single-page programming mode; verifying the plurality of data stored in the first physical erasing unit; and if the verification fails, performing a writing operation to a third physical erasing unit by using the multi-page programming mode according to the at least one first data and the plurality of data.

公开(公告)号：US20200379654A1

公开(公告)日：2020-12-03

申请号：US16529807

申请日：2019-08-02

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Hsiao-Yi Lin ,  Yu-Siang Yang

IPC: G06F3/06 ,  G11C16/26

Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a first physical unit among a plurality of physical units based on a first electrical configuration to obtain first soft information; reading the first physical unit based on a second electrical configuration which is different from the first electrical configuration to obtain second soft information; classifying a plurality of memory cells in the first physical unit according to the first soft information and the second soft information; and decoding data read from the first physical unit according to a classification result of the memory cells.

公开(公告)号：US10522234B2

公开(公告)日：2019-12-31

申请号：US15890326

申请日：2018-02-06

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Hsiang Lin ,  Yu-Cheng Hsu

IPC: G11C29/00 ,  G11C16/34 ,  G06F11/10 ,  G11C16/10 ,  G11C29/52 ,  G11C16/26

Abstract: A bit tagging method, a memory control circuit unit and a memory storage device are provided. The method includes: reading first memory cells according to a first reading voltage to generate a first codeword and determining whether the first codeword is a valid codeword, and the first codeword includes X bits; if not, reading the first memory cells according to a second reading voltage to generate a second codeword and determining whether the second codeword is the valid codeword, and the second codeword includes X bits; and if the second codeword is not the valid codeword and a Yth bit in the X bits of the first codeword is different from a Yth bit in the X bits of the second codeword, recording the Yth bit in the X bits as an unreliable bit, and Y is a positive integer less than or equal to X.

公开(公告)号：US10424391B2

公开(公告)日：2019-09-24

申请号：US15811695

申请日：2017-11-14

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Szu-Wei Chen ,  Yu-Siang Yang

IPC: G11C29/00 ,  G11C29/52 ,  G11C16/10 ,  G06F12/02 ,  G06F11/10 ,  G11C16/30 ,  G11C16/08 ,  G11C16/26 ,  G11C11/56 ,  G11C16/04

Abstract: A decoding method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: when first data is read from a first upper physical programming unit of a first physical programming unit group by using a second voltage selected from a first read voltage group, and a first error bit count of the first data is not greater than a first error bit count threshold, recording the second voltage; when a second data is read from a first lower physical programming unit of a second physical programming unit group by using a fourth voltage selected from a second read voltage group, and a second error bit count of the second data is not greater than a second error bit count threshold, recording the fourth voltage; generating a lookup table according to the second voltage and the fourth voltage; and performing a decoding operation according to the lookup table.

公开(公告)号：US20190189228A1

公开(公告)日：2019-06-20

申请号：US15890326

申请日：2018-02-06

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Hsiang Lin ,  Yu-Cheng Hsu

IPC: G11C16/34 ,  G06F11/10 ,  G11C29/52 ,  G11C16/26 ,  G11C16/10

Abstract: A bit tagging method, a memory control circuit unit and a memory storage device are provided. The method includes: reading first memory cells according to a first reading voltage to generate a first codeword and determining whether the first codeword is a valid codeword, and the first codeword includes X bits; if not, reading the first memory cells according to a second reading voltage to generate a second codeword and determining whether the second codeword is the valid codeword, and the second codeword includes X bits; and if the second codeword is not the valid codeword and a Yth bit in the X bits of the first codeword is different from a Yth bit in the X bits of the second codeword, recording the Yth bit in the X bits as an unreliable bit, and Y is a positive integer less than or equal to X.

公开(公告)号：US20180101317A1

公开(公告)日：2018-04-12

申请号：US15361008

申请日：2016-11-24

Applicant: PHISON ELECTRONICS CORP.

Inventor： Wei Lin ,  Yu-Cheng Hsu ,  Szu-Wei Chen

IPC: G06F3/06 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56 ,  G06F11/10 ,  G11C29/52

CPC classification number: G11C16/04 ,  G06F3/0619 ,  G06F11/1068 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/3459 ,  H03M13/2957

Abstract: The memory programming method includes: applying a first programming parameter set to program first data stream into a first physical programming unit, and the first physical programming unit is composed of memory cells at intersections between a first bit line string of a physical erasing unit and a first word line layer of the physical erasing unit. The memory programming method further includes applying a second programming parameter set to program the first data stream into all of the memory cells of the first physical programming unit again after completely programming the first data stream into all of the memory cells of the first physical programming unit.