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公开(公告)号：US11573704B2
公开(公告)日：2023-02-07
申请号：US16529807
申请日：2019-08-02
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Yu-Cheng Hsu , Hsiao-Yi Lin , Yu-Siang Yang
Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: reading a first physical unit among a plurality of physical units based on a first electrical configuration to obtain first soft information; reading the first physical unit based on a second electrical configuration which is different from the first electrical configuration to obtain second soft information; classifying a plurality of memory cells in the first physical unit according to the first soft information and the second soft information; and decoding data read from the first physical unit according to a classification result of the memory cells.
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公开(公告)号：US20220027089A1
公开(公告)日：2022-01-27
申请号：US16994668
申请日：2020-08-17
Applicant: PHISON ELECTRONICS CORP.
Inventor： Shih-Jia Zeng , Yu-Siang Yang , Szu-Wei Chen , Wei Lin
Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: determining a retry threshold value according to decoding history information which includes information related to at least one first decoding operation previously performed; and determining whether to enter a second decoding mode according to the retry threshold value after at least one second decoding operation performed based on a first decoding mode is failed. A decoding ability of the second decoding mode is higher than a decoding ability of the first decoding mode.
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公开(公告)号：US10978163B2
公开(公告)日：2021-04-13
申请号：US16601517
申请日：2019-10-14
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , An-Cheng Liu , Szu-Wei Chen , Yu-Siang Yang
Abstract: A voltage identifying method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a plurality of first memory cells according to a first read voltage group in a plurality of read voltage groups and performing a first decoding operation to generate first verification information; identifying a plurality of second read voltage groups in the plurality of read voltage groups corresponding to a first interval in a plurality of intervals according to the first interval in which the first verification information is located; and reading the plurality of first memory cells by using a third read voltage group in the plurality of second read voltage groups and performing the first decoding operation.
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公开(公告)号：US20200168289A1
公开(公告)日：2020-05-28
申请号：US16251105
申请日：2019-01-18
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , An-Cheng Liu , Yu-Cheng Hsu , Yu-Siang Yang
Abstract: A memory control method for a rewritable non-volatile memory module including a plurality of physical units is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first physical unit of a rewritable non-volatile memory module; decoding the first data by a decoding circuit; updating reliability information according to the decoded first data; reading second data from a second physical unit of the rewritable non-volatile memory module; and decoding the second data by the decoding circuit according to the updated reliability information.
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公开(公告)号：US20200034232A1
公开(公告)日：2020-01-30
申请号：US16120314
申请日：2018-09-03
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , An-Cheng Liu , Yu-Siang Yang , Yu-Cheng Hsu
Abstract: A bit determining method, a memory control circuit unit and a memory storage device are provided. The method includes: reading a first storage state of a first memory cell to obtain a first value of a first significant bit; reading the first storage state of the first memory cell to obtain at least one second value of at least one second significant bit; performing a first decoding operation according to the at least one second value to obtain at least one third value of the decoded second significant bit; determining whether the first significant bit is a special bit according to the first storage state and a second storage state corresponding to the at least one third value; and if the first significant bit is the special bit, performing a corresponding decoding operation.
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Patent Agency Ranking
公开(公告)号：US10074433B1
公开(公告)日：2018-09-11
申请号：US15786604
申请日：2017-10-18
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Cheng Hsu , Wei Lin , Yu-Siang Yang
CPC classification number: G11C16/107 , G11C7/1006 , G11C7/1045 , G11C16/08 , G11C16/10 , G11C16/24
Abstract: A data encoding method, a memory control circuit unit and a memory storage device are provided. The method includes: writing a first data into a first physical programming unit of a first physical programming unit group among a plurality of physical programming unit groups; writing a second data into a second physical programming unit of a second physical programming unit group among the plurality of physical programming unit groups; encoding the first data and the second data to generate an encoded data; and writing the encoded data into a third physical programming unit group among the plurality of physical programming unit groups.
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公开(公告)号：US11726709B2
公开(公告)日：2023-08-15
申请号：US16994668
申请日：2020-08-17
Applicant: PHISON ELECTRONICS CORP.
Inventor： Shih-Jia Zeng , Yu-Siang Yang , Szu-Wei Chen , Wei Lin
CPC classification number: G06F3/0659 , G06F3/0604 , G06F3/0679 , G11C16/26 , G11C16/0483
Abstract: A memory control method, a memory storage device and a memory control circuit unit are provided. The method includes: determining a retry threshold value according to decoding history information which includes information related to at least one first decoding operation previously performed; and determining whether to enter a second decoding mode according to the retry threshold value after at least one second decoding operation performed based on a first decoding mode is failed. A decoding ability of the second decoding mode is higher than a decoding ability of the first decoding mode.
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公开(公告)号：US20220365706A1
公开(公告)日：2022-11-17
申请号：US17336347
申请日：2021-06-02
Applicant: PHISON ELECTRONICS CORP.
Inventor： Yu-Siang Yang , Wei Lin , Shih-Jia Zeng , An-Cheng Liu , Yu-Cheng Hsu
IPC: G06F3/06
Abstract: A data accessing method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a codeword stored in a physical programming unit, and calculating a bit change ratio of a bit value change in dummy data included in the codeword; adjusting a read voltage level or a log likelihood ratio according to the bit change ratio; and performing a decoding operation on the codeword by using the adjusted read voltage level or the adjusted log likelihood ratio.
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公开(公告)号：US20210082522A1
公开(公告)日：2021-03-18
申请号：US16601517
申请日：2019-10-14
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , An-Cheng Liu , Szu-Wei Chen , Yu-Siang Yang
Abstract: A voltage identifying method, a memory controlling circuit unit, and a memory storage device are provided. The method includes: reading a plurality of first memory cells according to a first read voltage group in a plurality of read voltage groups and performing a first decoding operation to generate first verification information; identifying a plurality of second read voltage groups in the plurality of read voltage groups corresponding to a first interval in a plurality of intervals according to the first interval in which the first verification information is located; and reading the plurality of first memory cells by using a third read voltage group in the plurality of second read voltage groups and performing the first decoding operation.
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公开(公告)号：US20200183623A1
公开(公告)日：2020-06-11
申请号：US16258693
申请日：2019-01-28
Applicant: PHISON ELECTRONICS CORP.
Inventor： Wei Lin , Yu-Cheng Hsu , Szu-Wei Chen , Yu-Siang Yang
Abstract: A memory control method for a rewritable non-volatile memory module is provided according to an exemplary embodiment of the disclosure. The method includes: reading first data from a first memory cell of the rewritable non-volatile memory module by a first read voltage level; decoding the first data by a decoding circuit; reading second data from the first memory cell by a second read voltage level; obtaining reliability information according to a first data status of the first data and a second data status of the second data, and the first data status and the second data status reflect that a first bit value of the first data is different from a second bit value of the second data; and decoding the second data by the decoding circuit according to the reliability information.
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