公开(公告)号：US09379043B1

公开(公告)日：2016-06-28

申请号：US14618790

申请日：2015-02-10

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Ming-Yi Wang ,  Chao-Shun Chiu ,  Yen-Chu Chen

IPC: H01L21/76 ,  H01L29/49 ,  H01L23/48 ,  H01L23/00 ,  H01L23/532 ,  H01L23/31 ,  H01L21/764 ,  H01L21/768

CPC classification number: H01L23/481 ,  H01L21/764 ,  H01L21/7682 ,  H01L21/76898 ,  H01L23/3171 ,  H01L24/11 ,  H01L24/13 ,  H01L29/4991 ,  H01L2221/1047 ,  H01L2224/11462 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/01082 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Disclosed is a TSV structure having insulating layers with embedded voids, including a chip layer, a dielectric liner and a conductive filler. There is at least a via reentrant from one surface of the semiconductor body of the chip layer. A plurality of air-gap cavities are formed on the sidewall of the via where the cavities have a depth-to-width ratio not less than one. The dielectric liner covers the sidewall of the via without filling into the air-gap cavities. The conductive filler is disposed in the via without filling into the air-gap cavities due to the isolation of the dielectric liner so as to form an air insulating layer with a plurality of enclosed voids embedded between the semiconductor body and the dielectric liner. Accordingly, RC Delay of the TSV structure can be improved.

Abstract translation: 公开了具有包含芯片层，电介质衬垫和导电填料的具有嵌入空隙的绝缘层的TSV结构。 从芯片层的半导体主体的一个表面至少存在通孔折返。 在通孔的侧壁上形成有多个气隙腔，其中空腔具有不小于1的深度 - 宽度比。 电介质衬垫覆盖通孔的侧壁而不填充到气隙腔中。 导电填料由于绝缘衬垫的隔离而设置在通孔中，而不会填充到气隙腔中，从而形成具有嵌入在半导体本体和电介质衬垫之间的多个封闭空隙的空气绝缘层。 因此，可以提高TSV结构的RC延迟。