公开(公告)号：US11587808B2

公开(公告)日：2023-02-21

申请号：US16998266

申请日：2020-08-20

Applicant: Powertech Technology Inc.

Inventor： Shih-Chun Chen ,  Sheng-Tou Tseng ,  Kun-Chi Hsu ,  Chin-Ta Wu ,  Ying-Lin Chen ,  Ting-Yeh Wu

IPC: H01L21/673 ,  C23C14/56

Abstract: A chip carrier device includes a frame, a chip support and a limiter. The chip support is disposed on the frame, and includes a supporting film for chips to be adhered thereto. A peripheral portion of the supporting film is attached to a surrounding frame part of the frame. A crossing portion of the supporting film passes through a center of the supporting film, and interconnects two opposite points of the peripheral portion. The supporting film is formed with through holes. The limiter includes a limiting part that interconnects two opposite points of the surrounding frame part, that is positioned corresponding to the crossing portion, and that is positioned on one side of the supporting film where the chips are to be arranged.

公开(公告)号：US11410945B2

公开(公告)日：2022-08-09

申请号：US17094101

申请日：2020-11-10

Applicant: Powertech Technology Inc.

Inventor： Shih-Chun Chen ,  Sheng-Tou Tseng ,  Kun-Chi Hsu ,  Chin-Ta Wu ,  Ying-Lin Chen ,  Ting-Yeh Wu

IPC: H01L23/66 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L21/56 ,  H01Q1/22

Abstract: A semiconductor package having a partial outer metal layer and packaging method thereof is disclosed. In the method, a specific packaging substrate or a specific positioning plate is used to package multiple semiconductor devices and a partial outer metal layer is quickly formed on an encapsulation of each semiconductor device in the same step.

公开(公告)号：US10388535B1

公开(公告)日：2019-08-20

申请号：US15989203

申请日：2018-05-25

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Chui-Liang Chiu ,  Kun-Chi Hsu ,  Jen-Tung Tseng ,  Chin-Ta Wu

IPC: H01L21/00 ,  H01L21/304 ,  H01L21/687 ,  H01L21/683 ,  H01L21/67

Abstract: A wafer processing method uses a chuck table with smaller diameter than a semiconductor wafer to be processed. A cut through edge trimming is therefore implemented on the periphery of the semiconductor wafer to form a cut through straight side at the periphery and also form a flat portion at the periphery as a positioning means for taping and backside grind processes.

公开(公告)号：US20190247944A1

公开(公告)日：2019-08-15

申请号：US15893684

申请日：2018-02-11

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Kun-Chi Hsu ,  Sheng-Tou Tseng ,  Hung-Chieh Huang

IPC: B23K1/20 ,  B23K3/08

CPC classification number: B23K1/203 ,  B23K1/0016 ,  B23K3/082 ,  B23K2101/40 ,  H05K3/3489

Abstract: A flux transfer tool includes a frame, a plunger, a baseplate, a flux supplier and a driving mechanism. The frame has a chamber. The plunger is movably disposed in the chamber. The baseplate is mounted on the frame. The baseplate has a plurality of holes formed thereon. The flux supplier is connected to the frame and contains a flux. The flux supplier supplies the flux to the chamber between the plunger and the baseplate. The driving mechanism is disposed on the frame. The driving mechanism drives the plunger to move towards the baseplate to squeeze the flux out of the holes of the baseplate. The driving mechanism drives the plunger to move away from the baseplate to keep the flux in the chamber.

公开(公告)号：US11658046B2

公开(公告)日：2023-05-23

申请号：US17094537

申请日：2020-11-10

Applicant: Powertech Technology Inc.

Inventor： Shih-Chun Chen ,  Sheng-Tou Tseng ,  Kun-Chi Hsu ,  Chin-Ta Wu ,  Ting-Yeh Wu

IPC: H01L23/552 ,  H01L21/56

CPC classification number: H01L21/561 ,  H01L21/568 ,  H01L23/552

Abstract: Batch semiconductor packaging structures with back-deposited shielding layer and manufacturing method are provided. A grid having multiple frames is glued on an adhesive substrate. Multiple semiconductor devices respectively align with corresponding frames and are stuck on the adhesive substrate. Then a metal layer covers the semiconductor devices and the grid. A distance between four peripheries of a bottom of each semiconductor device and the corresponding frame is smaller than a distance between the bottom and the adhesive substrate, so that the a portion of the metal layer extended to the peripheries of the bottom is effectively reduced during forming the metal layer. After the semiconductor devices are picked up, no metal scrap is remined thereon. Therefore, the adhesive substrate does not need to form openings in advance and is reusable. The grid is also reusable so the manufacturing cost of the present invention is decreased.

公开(公告)号：US20190275600A1

公开(公告)日：2019-09-12

申请号：US15915003

申请日：2018-03-07

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Kun-Chi Hsu ,  Sheng-Tou Tseng ,  Hung-Chieh Huang

IPC: B23K1/20 ,  H05K1/14 ,  H01L21/56 ,  H05K3/34 ,  H01L21/48 ,  H01L23/13 ,  H01L23/492 ,  H01L23/00

Abstract: A flux transfer tool includes a flux tray, a baseplate, a flux transfer head and a flexible member. The baseplate is disposed on the flux tray. The baseplate has a plurality of holes formed thereon. The flux transfer head is arranged corresponding to the flux tray and configured to move with respect to the flux tray. The flexible member is disposed on the flux transfer head. The flexible member faces the baseplate when the flux transfer head is located above the flux tray. When the holes are filled with a flux, the flux transfer head moves towards the flux tray, such that the flexible member adsorbs the flux from the holes.

公开(公告)号：US20190267346A1

公开(公告)日：2019-08-29

申请号：US15908759

申请日：2018-02-28

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Kun-Chi Hsu ,  Sheng-Tou Tseng ,  Hung-Chieh Huang

IPC: H01L23/00

Abstract: A flux transfer tool includes a heater, a flux supplier, an ejector and a baseplate. The heater has a nozzle. The flux supplier is connected to the heater and contains a flux. The ejector is connected to the heater. The baseplate has a plurality of first holes formed thereon. The flux supplier supplies the flux to the heater, the heater heats the flux, and the ejector ejects the flux from the nozzle to spray the flux on the baseplate.

公开(公告)号：US20190229064A1

公开(公告)日：2019-07-25

申请号：US15879305

申请日：2018-01-24

Applicant: Powertech Technology Inc.

Inventor： Chin-Ta Wu ,  Sheng-Tou Tseng ,  Kuo-Jhan Kao ,  Ying-Lin Chen ,  Cheng-Hung Song ,  Hung-Chieh Huang ,  Kun-Chi Hsu

IPC: H01L23/544 ,  H01L21/3205 ,  H01L21/268 ,  H01L23/31 ,  H01L21/285 ,  H01L21/321 ,  H01L23/552

Abstract: A laser color marking method for a semiconductor package has steps of: (a) providing a semiconductor element; (b) sputtering a metal layer on the semiconductor element; (c) obtaining a marking pattern; and (d) applying a laser light source on the marking region to form a mark according to the marking pattern. The mark is consisted of an optical oxide film converting ambient light to a corresponding color light, so a visible color mark is marked. Therefore, the present invention easily laser-marks the visible color mark on the semiconductor package.