公开(公告)号：US11522000B2

公开(公告)日：2022-12-06

申请号：US16856011

申请日：2020-04-22

Applicant: Powertech Technology Inc.

Inventor： Hung-Hsin Hsu ,  Wen-Hsiung Chang

IPC: H01L27/14 ,  H01L27/146

Abstract: A semiconductor package structure including a sensor die, a substrate, a light blocking layer, a circuit layer, a dam structure and an underfill is provided. The sensor die has a sensing surface. The sensing surface includes an image sensing area and a plurality of conductive bumps. The substrate is disposed on the sensing surface. The light blocking layer is located between the substrate and the sensor die. The circuit layer is disposed on the light blocking layer. The sensor die is electrically connected to the circuit layer by the conductive bumps. The dam structure is disposed on the substrate and surrounds the image sensing area. Opposite ends of the dam structure directly contact the sensor die and the light blocking layer. The underfill is disposed between the dam structure and the conductive bumps.

公开(公告)号：US20200091126A1

公开(公告)日：2020-03-19

申请号：US16687713

申请日：2019-11-19

Applicant: Powertech Technology Inc.

Inventor： Nan-Chun Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien ,  Wen-Hsiung Chang

IPC: H01L25/16 ,  H01L23/48 ,  H01L23/498 ,  H01L21/768 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package including a plurality of first chips, a plurality of through silicon vias, a least one insulator, a first circuit structure and a first encapsulant is provided. The first chip electrically connected to the through silicon vias includes a sensing area on a first active surface, a first back surface and a plurality of through holes extending from the first back surface towards the first active surface. The insulator is disposed on the first active surfaces of the first chips. The first circuit structure disposed on the first back surfaces of the first chips and electrically connected to the through silicon vias. The first encapsulant, laterally encapsulating the first chips.

公开(公告)号：US10424526B2

公开(公告)日：2019-09-24

申请号：US15782857

申请日：2017-10-13

Applicant: Powertech Technology Inc.

Inventor： Chi-An Wang ,  Hung-Hsin Hsu ,  Wen-Hsiung Chang

IPC: H01L23/31 ,  H01L21/52 ,  H01L23/055 ,  H01L21/288 ,  H01L21/48 ,  H01L21/56 ,  H01L23/498 ,  H01L23/12 ,  H01L23/488 ,  H01L23/00 ,  H01L23/16 ,  H01L21/60

Abstract: A chip package structure includes a redistribution layer, at least one chip, a reinforcing frame, an encapsulant and a plurality of solder balls. The redistribution layer includes a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the redistribution layer. The reinforcing frame is disposed on the first surface and includes at least one through cavity. The chip is disposed in the through cavity and a stiffness of the reinforcing frame is greater than a stiffness of the redistribution layer. The encapsulant encapsulates the chip, the reinforcing frame and covering the first surface. The solder balls are disposed on the second surface and electrically connected to the redistribution layer.

公开(公告)号：US20170256471A1

公开(公告)日：2017-09-07

申请号：US15432932

申请日：2017-02-15

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Li-Chih Fang ,  Chia-Chang Chang ,  Hung-Hsin Hsu ,  Wen-Hsiung Chang ,  Kee-Wei Chung ,  Chia-Wen Lien

IPC: H01L23/31 ,  H01L23/00 ,  H01L27/146 ,  H01L21/56 ,  H01L21/768 ,  H01L23/48 ,  H01L23/498

CPC classification number: H01L23/3114 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/83 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14636 ,  H01L2224/0237 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/13016 ,  H01L2224/13027 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2924/0132 ,  H01L2924/15311

Abstract: A wafer level chip scale package (WLCSP) has a device chip, a carrier chip, an offset pad, a conductive spacing bump and a through hole via (THV). The device chip is attached to the carrier chip. The offset pad is disposed on a first surface of the device chip. The conductive spacing bump is formed on the offset pad. The through hole via includes a through hole and a hole metal layer. The through hole penetrates through the carrier chip and the device chip, and the hole metal layer is formed in the through hole and in contact with the offset pad.

公开(公告)号：US11309296B2

公开(公告)日：2022-04-19

申请号：US16687713

申请日：2019-11-19

Applicant: Powertech Technology Inc.

Inventor： Nan-Chun Lin ,  Hung-Hsin Hsu ,  Shang-Yu Chang Chien ,  Wen-Hsiung Chang

IPC: H01L25/16 ,  H01L23/48 ,  H01L21/56 ,  H01L21/768 ,  H01L21/48 ,  H01L23/498 ,  H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L25/04 ,  H01L25/065

Abstract: A semiconductor package including a plurality of first chips, a plurality of through silicon vias, a least one insulator, a first circuit structure and a first encapsulant is provided. The first chip electrically connected to the through silicon vias includes a sensing area on a first active surface, a first back surface and a plurality of through holes extending from the first back surface towards the first active surface. The insulator is disposed on the first active surfaces of the first chips. The first circuit structure disposed on the first back surfaces of the first chips and electrically connected to the through silicon vias. The first encapsulant, laterally encapsulating the first chips.

公开(公告)号：US20210098517A1

公开(公告)日：2021-04-01

申请号：US16856011

申请日：2020-04-22

Applicant: Powertech Technology Inc.

Inventor： Hung-Hsin Hsu ,  Wen-Hsiung Chang

IPC: H01L27/146

Abstract: A semiconductor package structure including a sensor die, a substrate, a light blocking layer, a circuit layer, a dam structure and an underfill is provided. The sensor die has a sensing surface. The sensing surface includes an image sensing area and a plurality of conductive bumps. The substrate is disposed on the sensing surface. The light blocking layer is located between the substrate and the sensor die. The circuit layer is disposed on the light blocking layer. The sensor die is electrically connected to the circuit layer by the conductive bumps. The dam structure is disposed on the substrate and surrounds the image sensing area. Opposite ends of the dam structure directly contact the sensor die and the light blocking layer. The underfill is disposed between the dam structure and the conductive bumps.

公开(公告)号：US20190096866A1

公开(公告)日：2019-03-28

申请号：US15715169

申请日：2017-09-26

Applicant: Powertech Technology Inc.

Inventor： Ching-Ming Hsu ,  Wen-Hsiung Chang ,  Po-Wei Yeh ,  Yun-Hsin Yeh

IPC: H01L25/18 ,  H01L21/768 ,  H01L23/48 ,  H01L23/31 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor package including a first semiconductor chip, a plurality of first conductors, a first conductive pattern electrically connected to the first conductors, a second semiconductor chip disposed on the first semiconductor chip, and an encapsulant on the first conductive pattern and laterally encapsulating the second semiconductor chip. The first semiconductor chip electrically connected to the first conductors includes a sensing area on a first active surface, a first back surface and a plurality of through holes extending form the first back surface towards the first active surface. The second semiconductor chip including a second active surface facing towards the first back surface electrically connects the first semiconductor chip through the first conductors in the through holes and the first conductive pattern on the first back surface. A manufacturing method of a semiconductor package is also provided.

公开(公告)号：US20180114734A1

公开(公告)日：2018-04-26

申请号：US15782857

申请日：2017-10-13

Applicant: Powertech Technology Inc.

Inventor： Chi-An Wang ,  Hung-Hsin Hsu ,  Wen-Hsiung Chang

IPC: H01L23/12 ,  H01L23/31 ,  H01L23/488 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48

Abstract: A chip package structure includes a redistribution layer, at least one chip, a reinforcing frame, an encapsulant and a plurality of solder balls. The redistribution layer includes a first surface and a second surface opposite to each other. The chip is disposed on the first surface and electrically connected to the redistribution layer. The reinforcing frame is disposed on the first surface and includes at least one through cavity. The chip is disposed in the through cavity and a stiffness of the reinforcing frame is greater than a stiffness of the redistribution layer. The encapsulant encapsulates the chip, the reinforcing frame and covering the first surface. The solder balls are disposed on the second surface and electrically connected to the redistribution layer.

公开(公告)号：US20210098324A1

公开(公告)日：2021-04-01

申请号：US16583286

申请日：2019-09-26

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Hung-Hsin Hsu ,  Wen-Hsiung Chang

IPC: H01L23/31 ,  H01L27/146 ,  H01L21/768

Abstract: By using a photosensitive material coating or laminating on the substrate, an opening well structure with plurality of openings and pillars is formed by photolithography or mechanical processing to have patterns corresponding to the active sensor areas of the chip die so as to provide improved support on the substrate for the cover glass. The overall package structure is then reinforced without the risk of cracking the substrate.

公开(公告)号：US09972554B2

公开(公告)日：2018-05-15

申请号：US15432932

申请日：2017-02-15

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Li-Chih Fang ,  Chia-Chang Chang ,  Hung-Hsin Hsu ,  Wen-Hsiung Chang ,  Kee-Wei Chung ,  Chia-Wen Lien

IPC: H01L29/40 ,  H01L23/52 ,  H01L23/48 ,  H01L23/31 ,  H01L21/56 ,  H01L21/768 ,  H01L23/498 ,  H01L23/00 ,  H01L27/146

CPC classification number: H01L23/3114 ,  H01L21/56 ,  H01L21/76898 ,  H01L23/3121 ,  H01L23/481 ,  H01L23/49827 ,  H01L23/562 ,  H01L24/03 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L24/32 ,  H01L24/83 ,  H01L27/14618 ,  H01L27/14627 ,  H01L27/14632 ,  H01L27/14636 ,  H01L2224/0237 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/1134 ,  H01L2224/11462 ,  H01L2224/13016 ,  H01L2224/13027 ,  H01L2224/13139 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2924/0132 ,  H01L2924/15311

Abstract: A wafer level chip scale package (WLCSP) has a device chip, a carrier chip, an offset pad, a conductive spacing bump and a through hole via (THV). The device chip is attached to the carrier chip. The offset pad is disposed on a first surface of the device chip. The conductive spacing bump is formed on the offset pad. The through hole via includes a through hole and a hole metal layer. The through hole penetrates through the carrier chip and the device chip, and the hole metal layer is formed in the through hole and in contact with the offset pad.