公开(公告)号：US20190189816A1

公开(公告)日：2019-06-20

申请号：US16228441

申请日：2018-12-20

Applicant: PsiQuantum Corp.

Inventor： Faraz Najafi ,  Mark Thompson ,  Damien Bonneau ,  Joaquin Matres Abril

IPC: H01L31/0352 ,  H01L31/109 ,  H01L31/0232 ,  H01L31/18

CPC classification number: H01L31/035227 ,  G01J1/42 ,  G02B6/1226 ,  H01L31/02327 ,  H01L31/109 ,  H01L31/18 ,  H01L39/10 ,  H01L39/24 ,  H01L39/2406

Abstract: A device includes a first semiconductor layer; a portion of a second semiconductor layer disposed on the first semiconductor layer; and a third semiconductor layer including a first region disposed on the portion of the second semiconductor layer and a second region disposed on the first semiconductor layer. A thickness of the first region is less than a predefined thickness. The device also includes an etch stop layer disposed on the third semiconductor layer; a plurality of distinct portions of a fourth semiconductor layer disposed on the etch stop layer and exposing one or more distinct portions of the etch stop layer over the portion of the second semiconductor layer; and a plurality of distinct portions of a superconducting layer disposed on the plurality of distinct portions of the fourth semiconductor layer and the exposed one or more distinct portions of the etch stop layer.

公开(公告)号：US11658254B2

公开(公告)日：2023-05-23

申请号：US17688769

申请日：2022-03-07

Applicant: PSIQUANTUM CORP.

Inventor： Faraz Najafi ,  Mark Thompson ,  Damien Bonneau ,  Joaquin Matres Abril

IPC: H01L31/0352 ,  H01L31/18 ,  H01L31/0232 ,  H01L31/109 ,  H01L39/24 ,  G01J1/42 ,  H01L39/10 ,  G01J1/44

CPC classification number: H01L31/035227 ,  G01J1/42 ,  G01J1/44 ,  H01L31/02327 ,  H01L31/109 ,  H01L31/18 ,  H01L39/10 ,  H01L39/24 ,  H01L39/2416 ,  G01J2001/442

Abstract: A device includes a first semiconductor layer; a portion of a second semiconductor layer disposed on the first semiconductor layer; and a third semiconductor layer including a first region disposed on the portion of the second semiconductor layer and a second region disposed on the first semiconductor layer. A thickness of the first region is less than a predefined thickness. The device also includes an etch stop layer disposed on the third semiconductor layer; a plurality of distinct portions of a fourth semiconductor layer disposed on the etch stop layer and exposing one or more distinct portions of the etch stop layer over the portion of the second semiconductor layer; and a plurality of distinct portions of a superconducting layer disposed on the plurality of distinct portions of the fourth semiconductor layer and the exposed one or more distinct portions of the etch stop layer.

公开(公告)号：US11271125B2

公开(公告)日：2022-03-08

申请号：US16848662

申请日：2020-04-14

Applicant: PSIQUANTUM CORP.

Inventor： Faraz Najafi ,  Mark Thompson ,  Damien Bonneau ,  Joaquin Matres Abril

IPC: H01L31/0352 ,  H01L31/18 ,  H01L31/0232 ,  H01L31/109 ,  H01L39/24 ,  G01J1/42 ,  H01L39/10 ,  G01J1/44

Abstract: A device includes a first semiconductor layer; a portion of a second semiconductor layer disposed on the first semiconductor layer; and a third semiconductor layer including a first region disposed on the portion of the second semiconductor layer and a second region disposed on the first semiconductor layer. A thickness of the first region is less than a predefined thickness. The device also includes an etch stop layer disposed on the third semiconductor layer; a plurality of distinct portions of a fourth semiconductor layer disposed on the etch stop layer and exposing one or more distinct portions of the etch stop layer over the portion of the second semiconductor layer; and a plurality of distinct portions of a superconducting layer disposed on the plurality of distinct portions of the fourth semiconductor layer and the exposed one or more distinct portions of the etch stop layer.

公开(公告)号：US10651325B2

公开(公告)日：2020-05-12

申请号：US16228441

申请日：2018-12-20

Applicant: PsiQuantum Corp.

Inventor： Faraz Najafi ,  Mark Thompson ,  Damien Bonneau ,  Joaquin Matres Abril

IPC: H01L31/0352 ,  H01L31/18 ,  H01L31/0232 ,  H01L31/109 ,  H01L39/24 ,  G01J1/42 ,  H01L39/10 ,  G01J1/44

Abstract: A device includes a first semiconductor layer; a portion of a second semiconductor layer disposed on the first semiconductor layer; and a third semiconductor layer including a first region disposed on the portion of the second semiconductor layer and a second region disposed on the first semiconductor layer. A thickness of the first region is less than a predefined thickness. The device also includes an etch stop layer disposed on the third semiconductor layer; a plurality of distinct portions of a fourth semiconductor layer disposed on the etch stop layer and exposing one or more distinct portions of the etch stop layer over the portion of the second semiconductor layer; and a plurality of distinct portions of a superconducting layer disposed on the plurality of distinct portions of the fourth semiconductor layer and the exposed one or more distinct portions of the etch stop layer.