In-memory bit-serial addition system

    公开(公告)号:US11669302B2

    公开(公告)日:2023-06-06

    申请号:US17071930

    申请日:2020-10-15

    CPC classification number: G06F7/5052 G06F7/4912 G06F7/74 G06F17/16

    Abstract: An in-memory vector addition method for a dynamic random access memory (DRAM) is disclosed which includes consecutively transposing two numbers across a plurality of rows of the DRAM, each number transposed across a fixed number of rows associated with a corresponding number of bits, assigning a scratch-pad including two consecutive bits for each bit of each number being added, two consecutive bits for carry-in (Cin), and two consecutive bits for carry-out-bar (Cout), assigning a plurality of bits in a transposed orientation to hold results as a sum of the two numbers, for each bit position of the two numbers: computing the associated sum of the bit position; and placing the computed sum in the associated bit of the sum.

    IN-MEMORY BIT-SERIAL ADDITION SYSTEM

    公开(公告)号:US20210117156A1

    公开(公告)日:2021-04-22

    申请号:US17071930

    申请日:2020-10-15

    Abstract: An in-memory vector addition method for a dynamic random access memory (DRAM) is disclosed which includes consecutively transposing two numbers across a plurality of rows of the DRAM, each number transposed across a fixed number of rows associated with a corresponding number of bits, assigning a scratch-pad including two consecutive bits for each bit of each number being added, two consecutive bits for carry-in (Cin), and two consecutive bits for carry-out-bar (Cout), assigning a plurality of bits in a transposed orientation to hold results as a sum of the two numbers, for each bit position of the two numbers: computing the associated sum of the bit position; and placing the computed sum in the associated bit of the sum.

    In-memory bit-serial addition system

    公开(公告)号:US12118328B2

    公开(公告)日:2024-10-15

    申请号:US18205528

    申请日:2023-06-03

    CPC classification number: G06F7/5052 G06F7/4912 G06F7/74 G06F17/16

    Abstract: An in-memory vector addition method for a dynamic random access memory (DRAM) is disclosed which includes consecutively transposing two numbers across a plurality of rows of the DRAM, each number transposed across a fixed number of rows associated with a corresponding number of bits, assigning a scratch-pad including two consecutive bits for each bit of each number being added, two consecutive bits for carry-in (Cin), and two consecutive bits for carry-out-bar (Cout), assigning a plurality of bits in a transposed orientation to hold results as a sum of the two numbers, for each bit position of the two numbers: computing the associated sum of the bit position; and placing the computed sum in the associated bit of the sum.

    IN-MEMORY BIT-SERIAL ADDITION SYSTEM
    4.
    发明公开

    公开(公告)号:US20230305804A1

    公开(公告)日:2023-09-28

    申请号:US18205528

    申请日:2023-06-03

    CPC classification number: G06F7/5052 G06F17/16 G06F7/74 G06F7/4912

    Abstract: An in-memory vector addition method for a dynamic random access memory (DRAM) is disclosed which includes consecutively transposing two numbers across a plurality of rows of the DRAM, each number transposed across a fixed number of rows associated with a corresponding number of bits, assigning a scratch-pad including two consecutive bits for each bit of each number being added, two consecutive bits for carry-in (Cin), and two consecutive bits for carry-out-bar (Cout), assigning a plurality of bits in a transposed orientation to hold results as a sum of the two numbers, for each bit position of the two numbers: computing the associated sum of the bit position; and placing the computed sum in the associated bit of the sum.

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