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    SPIN ORBIT TORQUE BASED ELECTRONIC NEURON
    1.
    发明申请
    SPIN ORBIT TORQUE BASED ELECTRONIC NEURON 有权

    公开(公告)号：US20210142157A1

    公开(公告)日：2021-05-13

    申请号：US16999049

    申请日：2020-08-20

    Applicant: Purdue Research Foundation

    Inventor： Abhronil Sengupta ,  Sri Harsha Choday ,  Yusung Kim ,  Kaushik Roy

    IPC: G06N3/063 ,  H01L43/08 ,  H01L43/06 ,  G06F7/58 ,  G06N3/04 ,  G06F7/48 ,  H01L27/24

    Abstract: An electronic neuron device that includes a thresholding unit which utilizes current-induced spin-orbit torque (SOT). A two-step switching scheme is implemented with the device. In the first step, a charge current through heavy metal (HM) places the magnetization of a nano-magnet along the hard-axis (i.e. an unstable point for the magnet). In the second step, the device receives a current (from an electronic synapse) which moves the magnetization from the unstable point to one of the two stable states. The polarity of the net synaptic current determines the final orientation of the magnetization. A resistive crossbar array may also be provided which functions as the synapse generating a bipolar current that is a weighted sum of the inputs of the device.

    Multi-bit dot product engine
    2.
    发明授权
    Multi-bit dot product engine 有权

    公开(公告)号：US10825510B2

    公开(公告)日：2020-11-03

    申请号：US16271811

    申请日：2019-02-09

    Applicant: Purdue Research Foundation

    Inventor： Akhilesh Ramlaut Jaiswal ,  Amogh Agrawal ,  Kaushik Roy ,  Indranil Chakraborty

    IPC: G11C11/419 ,  G06F17/16 ,  G11C11/412 ,  G11C7/18 ,  G11C7/06

    Abstract: A method of obtaining an in-memory vector-based dot product is disclosed, which includes providing a matrix of memory cells having M rows, each memory cell in each row holding a value and having dedicated read transistors T1 and T2, where T1 is controlled by the value held in the associated memory cell and T2 is controlled by a row-dedicated source (vin) for each row, the combination of the T1 and T2 transistors for each cell selectively (i) couple a reference voltage with a column-dedicated read bit line (RBL) for each column for an in-memory vector-based dot product operation or (ii) couple ground with the column-dedicated read bit line (RBL) for each column for a memory read operation, where total resistance of the read transistors (R) for each cell in each row is based on Rmax/2(M-1), . . . Rmax, where Rmax is the resistance of the least significant cell in each row.

    MULTI-BIT DOT PRODUCT ENGINE
    3.
    发明申请
    MULTI-BIT DOT PRODUCT ENGINE 审中-公开

    公开(公告)号：US20200258569A1

    公开(公告)日：2020-08-13

    申请号：US16271811

    申请日：2019-02-09

    Applicant: Purdue Research Foundation

    Inventor： Akhilesh Ramlaut Jaiswal ,  Amogh Agrawal ,  Kaushik Roy ,  Indranil Chakraborty

    IPC: G11C11/419 ,  G11C11/412 ,  G06F17/16

    Abstract: A method of obtaining an in-memory vector-based dot product is disclosed, which includes providing a matrix of memory cells having M rows, each memory cell in each row holding a value and having dedicated read transistors T1 and T2, where T1 is controlled by the value held in the associated memory cell and T2 is controlled by a row-dedicated source (vin) for each row, the combination of the T1 and T2 transistors for each cell selectively (i) couple a reference voltage with a column-dedicated read bit line (RBL) for each column for an in-memory vector-based dot product operation or (ii) couple ground with the column-dedicated read bit line (RBL) for each column for a memory read operation, where total resistance of the read transistors (R) for each cell in each row is based on Rmax/2(M-1), . . . Rmax, where Rmax is the resistance of the least significant cell in each row.

    Approximate cache memory
    6.
    发明授权
    Approximate cache memory 有权

    公开(公告)号：US10255186B2

    公开(公告)日：2019-04-09

    申请号：US15623343

    申请日：2017-06-14

    Applicant: Purdue Research Foundation

    Inventor： Ashish Ranjan ,  Swagath Venkataramani ,  Zoha Pajouhi ,  Rangharajan Venkatesan ,  Kaushik Roy ,  Anand Raghunathan

    IPC: G06F12/08 ,  G06F12/0846 ,  G06F12/0891

    Abstract: An approximate cache system is disclosed. The system includes a quality aware cache controller (QACC), a cache, a quality table configured to receive addresses and a quality specification from the processor associated with each address and further configured to provide the quality specification for each address to the QACC, wherein the QACC controls approximation is based on one or more of i) approximation through partial read operations; ii) approximation through lower read currents; iii) approximation through skipped write operations; iv) approximation through partial write operations; v) approximations through lower write duration; vi) approximation through lower write currents; and vii) approximations through skipped refreshes.

    Electronic memory including ROM and RAM
    9.
    发明授权
    Electronic memory including ROM and RAM 有权
    电子存储器包括ROM和RAM

    公开(公告)号：US09552859B2

    公开(公告)日：2017-01-24

    申请号：US14723450

    申请日：2015-05-27

    Applicant: Purdue Research Foundation

    Inventor： Kaushik Roy ,  Dongsoo Lee ,  Xuanyao Fong

    IPC: G11C11/00 ,  G11C11/16

    CPC classification number: G11C11/1673 ,  G11C11/1655 ,  G11C11/1659

    Abstract: An electronic data-storage apparatus having ROM embedded in an STT-MRAM. The apparatus comprises at least two bit lines, a plurality of bit cells, each including, connected to a source line (SL), a series connection (in any order) of a selection element (e.g., transistor gated by word line WL), a resistive storage element (e.g., MTJ), and a permanent connection to one of the bit lines (e.g., BL0, BL1). The apparatus may also include a ROM sense amplifier which is configured to precharge two output nodes connected to respective ones of the bit lines, so that the jumper in a selected memory cell pulls one of the output nodes to a first reference potential (e.g., GND) and the ROM sense amplifier pulls the other of the output nodes to a second reference potential (e.g., Vdd).

    Abstract translation: 具有嵌入在STT-MRAM中的ROM的电子数据存储装置。 该装置包括至少两个位线，多个位单元，每个位单元包括连接到源极线（SL）的选择元件（例如，由字线WL栅极控制的晶体管）的串联连接（以任何顺序） 电阻存储元件（例如，MTJ）以及与位线之一（例如，BL0，BL1）的永久连接。 该装置还可以包括ROM读出放大器，其被配置为对连接到相应位线的两个输出节点进行预充电，使得所选择的存储器单元中的跳线将输出节点之一拉到第一参考电位（例如，GND ），并且ROM读出放大器将另一个输出节点拉到第二参考电位（例如，Vdd）。

    Spin orbit torque based electronic neuron
    10.
    发明授权
    Spin orbit torque based electronic neuron 有权

    公开(公告)号：US12141686B2

    公开(公告)日：2024-11-12

    申请号：US16999049

    申请日：2020-08-20

    Applicant: Purdue Research Foundation

    Inventor： Abhronil Sengupta ,  Sri Harsha Choday ,  Yusung Kim ,  Kaushik Roy

    IPC: H01L43/08 ,  G06F7/58 ,  G06N3/04 ,  G06N3/065 ,  H10B63/00 ,  H10N50/10 ,  H10N52/00 ,  G11C11/54 ,  H10B61/00

    Abstract: An electronic neuron device that includes a thresholding unit which utilizes current-induced spin-orbit torque (SOT). A two-step switching scheme is implemented with the device. In the first step, a charge current through heavy metal (HM) places the magnetization of a nano-magnet along the hard-axis (i.e. an unstable point for the magnet). In the second step, the device receives a current (from an electronic synapse) which moves the magnetization from the unstable point to one of the two stable states. The polarity of the net synaptic current determines the final orientation of the magnetization. A resistive crossbar array may also be provided which functions as the synapse generating a bipolar current that is a weighted sum of the inputs of the device.

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