公开(公告)号：US09786613B2

公开(公告)日：2017-10-10

申请号：US14454204

申请日：2014-08-07

Applicant: QUALCOMM Incorporated

Inventor： Michael A. Stuber

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/60 ,  H01L21/84 ,  H01L23/552 ,  H01L21/683

CPC classification number: H01L23/60 ,  H01L21/6835 ,  H01L21/76256 ,  H01L21/76838 ,  H01L21/78 ,  H01L21/84 ,  H01L23/552 ,  H01L23/64 ,  H01L23/66 ,  H01L25/16 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2223/6616 ,  H01L2223/6672 ,  H01L2924/0002 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1421 ,  H01L2924/1461 ,  H01L2924/00

Abstract: Various methods and devices that involve EMI shields for radio frequency layer transferred devices are disclosed. One method comprises forming a radio frequency field effect transistor in an active layer of a semiconductor on insulator wafer. The semiconductor on insulator wafer has a buried insulator side and an active layer side. The method further comprises bonding a second wafer to the active layer side of the semiconductor on insulator wafer. The method further comprises forming a shield layer for the semiconductor device. The shield layer comprises an electrically conductive material. The method further comprises coupling the radio frequency field effect transistor to a circuit comprising a radio frequency component. The method further comprises singulating the radio frequency field effect transistor, radio frequency component, and the shield layer into a die. The shield layer is located between a substrate of the radio frequency component and the radio frequency field effect transistor.

公开(公告)号：US20170243887A1

公开(公告)日：2017-08-24

申请号：US15588945

申请日：2017-05-08

Applicant: QUALCOMM INCORPORATED

Inventor： Stuart B. Molin ,  Michael A. Stuber

IPC: H01L27/12 ,  H01L27/088 ,  H01L29/06 ,  H01L29/78 ,  H01L29/732 ,  H01L29/739 ,  H01L29/744 ,  H01L27/082 ,  H01L29/417

CPC classification number: H01L27/1203 ,  H01L21/6835 ,  H01L21/823487 ,  H01L21/84 ,  H01L23/481 ,  H01L24/11 ,  H01L24/13 ,  H01L24/14 ,  H01L24/94 ,  H01L27/0823 ,  H01L27/088 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/41741 ,  H01L29/66272 ,  H01L29/66333 ,  H01L29/66363 ,  H01L29/66712 ,  H01L29/66734 ,  H01L29/73 ,  H01L29/732 ,  H01L29/7395 ,  H01L29/744 ,  H01L29/7802 ,  H01L29/7812 ,  H01L29/7813 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2224/03002 ,  H01L2224/0401 ,  H01L2224/11002 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/94 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1305 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/014 ,  H01L2224/11 ,  H01L2924/00

Abstract: A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.

公开(公告)号：US20160359002A1

公开(公告)日：2016-12-08

申请号：US15241359

申请日：2016-08-19

Applicant: QUALCOMM Incorporated

Inventor： Paul A. Nygaard ,  Stuart B. Molin ,  Michael A. Stuber ,  Max Aubain

IPC: H01L29/10 ,  H01L23/367 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/1054 ,  H01L21/76256 ,  H01L21/78 ,  H01L21/84 ,  H01L23/36 ,  H01L23/3675 ,  H01L23/3677 ,  H01L24/03 ,  H01L24/08 ,  H01L24/11 ,  H01L24/13 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/80 ,  H01L24/83 ,  H01L24/94 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/1033 ,  H01L29/78 ,  H01L29/7843 ,  H01L29/7849 ,  H01L29/78603 ,  H01L29/78606 ,  H01L29/78654 ,  H01L2221/6834 ,  H01L2221/6835 ,  H01L2221/68377 ,  H01L2224/03845 ,  H01L2224/05572 ,  H01L2224/08225 ,  H01L2224/13022 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16227 ,  H01L2224/29186 ,  H01L2224/29188 ,  H01L2224/2919 ,  H01L2224/32225 ,  H01L2224/48 ,  H01L2224/80006 ,  H01L2224/8022 ,  H01L2224/80801 ,  H01L2224/80894 ,  H01L2224/83005 ,  H01L2224/8322 ,  H01L2224/83801 ,  H01L2224/8385 ,  H01L2224/9202 ,  H01L2224/9212 ,  H01L2224/92142 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/1305 ,  H01L2924/3011 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2924/053 ,  H01L2924/00012 ,  H01L2224/83 ,  H01L2224/80 ,  H01L2224/11 ,  H01L2224/03 ,  H01L2224/45099

Abstract: Embodiments of the present invention provide for the enhancement of transistors in a semiconductor structure using a strain layer. The structure comprises a patterned layer consisting of an excavated region and a pattern region, a strain layer located in the excavated region and on the pattern region, an active layer located above the strain layer, a field effect transistor formed in the active layer, and a handle layer located above the active layer. The field effect transistor comprises a source, a drain, and a channel. The channel lies completely within a lateral extent of the pattern region. The source and the drain each lie only partially within the lateral extent of the pattern region. The strain layer alters a carrier mobility of the channel. In some embodiments, the strain layer is introduced to the back side of a semiconductor-on-insulator structure.

Abstract translation: 本发明的实施例提供了使用应变层的半导体结构中的晶体管的增强。 该结构包括由挖掘区域和图案区域构成的图案层，位于挖掘区域和图案区域上的应变层，位于应变层上方的有源层，形成在有源层中的场效应晶体管，以及 位于有源层上方的手柄层。 场效应晶体管包括源极，漏极和沟道。 通道完全位于图案区域的横向范围内。 源极和漏极各自仅部分地位于图案区域的横向范围内。 应变层改变通道的载流子迁移率。 在一些实施例中，将应变层引入到绝缘体上半导体结构的背面。

公开(公告)号：US10211167B2

公开(公告)日：2019-02-19

申请号：US15154477

申请日：2016-05-13

Applicant: QUALCOMM Incorporated

Inventor： Michael A. Stuber

IPC: H01L21/4763 ,  H01L23/60 ,  H01L21/84 ,  H01L27/12 ,  H01L23/522 ,  H01L21/762 ,  H01L21/768 ,  H01L23/528 ,  H01L23/552 ,  H01L23/48

Abstract: An integrated circuit assembly is formed with an insulating layer, a semiconductor layer, an active device, first, second, and third electrically conductive interconnect layers, and a plurality of electrically conductive vias. The insulating layer has a first surface and a second surface. The second surface is below the first surface. A substrate layer has been removed from the second surface. The semiconductor layer has a first surface and a second surface. The first surface of the semiconductor layer contacts the first surface of the insulating layer. The active device is formed in a region of the semiconductor layer. The first electrically conductive interconnect layer forms an electrically conductive ring. The second electrically conductive interconnect layer forms a first electrically conductive plate above the electrically conductive ring and the region of the semiconductor layer. The third electrically conductive interconnect layer forms a second electrically conductive plate below the electrically conductive ring and the region of the semiconductor layer. The plurality of electrically conductive vias electrically couple the electrically conductive ring to the first electrically conductive plate and to the second electrically conductive plate. The electrically conductive ring, the first electrically conductive plate, the second electrically conductive plate, and the plurality of electrically conductive vias form a Faraday cage around the active device.

公开(公告)号：US09624096B2

公开(公告)日：2017-04-18

申请号：US14454370

申请日：2014-08-07

Applicant: QUALCOMM Incorporated

Inventor： Michael A. Stuber

IPC: H01L29/00 ,  B81C1/00 ,  B81B7/00 ,  H01L21/20 ,  H01L21/768 ,  H01L21/84 ,  H01L23/48 ,  H01L29/78 ,  H01L27/12 ,  H01L21/762

CPC classification number: B81C1/00158 ,  B81B3/0021 ,  B81B7/008 ,  B81B2203/0127 ,  B81C1/00269 ,  B81C2201/0194 ,  B81C2203/037 ,  H01L21/2007 ,  H01L21/76256 ,  H01L21/76898 ,  H01L21/7806 ,  H01L21/84 ,  H01L23/481 ,  H01L25/00 ,  H01L27/1203 ,  H01L29/7803 ,  H01L2924/0002 ,  H01L2924/1461 ,  H01L2224/9202 ,  H01L2924/00

Abstract: A semiconductor wafer is formed with a first device layer having active devices. A handle wafer having a trap rich layer is bonded to a top surface of the semiconductor wafer. A second device layer having a MEMS device or acoustic filter device is formed on a bottom surface of the semiconductor wafer. The second device layer is formed either by monolithic fabrication processes or layer-transfer processes.

公开(公告)号：US10431598B2

公开(公告)日：2019-10-01

申请号：US15588945

申请日：2017-05-08

Applicant: QUALCOMM INCORPORATED

Inventor： Stuart B. Molin ,  Michael A. Stuber

IPC: H01L27/12 ,  H01L27/082 ,  H01L27/088 ,  H01L29/06 ,  H01L29/66 ,  H01L29/732 ,  H01L21/8234 ,  H01L29/739 ,  H01L29/744 ,  H01L29/78 ,  H01L21/683 ,  H01L29/417 ,  H01L21/84 ,  H01L29/73 ,  H01L23/00 ,  H01L23/48

Abstract: A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.

公开(公告)号：US09553013B2

公开(公告)日：2017-01-24

申请号：US14633024

申请日：2015-02-26

Applicant: QUALCOMM Incorporated

Inventor： Michael A. Stuber ,  George Imthurn

IPC: H01L21/30 ,  H01L21/762 ,  H01L21/84 ,  H01L21/02 ,  H01L21/20 ,  H01L21/768 ,  H01L21/302 ,  H01L23/48 ,  H01L29/78 ,  H01L27/12 ,  B81C1/00

CPC classification number: H01L21/76251 ,  B81C1/00238 ,  B81C1/00698 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/02178 ,  H01L21/2007 ,  H01L21/302 ,  H01L21/76224 ,  H01L21/76256 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L27/1203 ,  H01L29/7803 ,  H01L2224/80001 ,  H01L2224/9202 ,  H01L2924/1461 ,  H01L2924/00

Abstract: A method is disclosed. The method comprises fabricating a device layer on a top portion of a semiconductor wafer that comprises a substrate. The device layer comprises an active device. The method also comprises forming a trap rich layer at a top portion of a handle wafer. The forming comprises etching the top portion of the handle wafer to form a structure in the top portion of the handle wafer that configures the trap rich layer. The method also comprises bonding a top surface of the handle wafer to a top surface of the semiconductor wafer. The method also comprises removing a bottom substrate portion of the semiconductor wafer.

Abstract translation: 公开了一种方法。 该方法包括在包括衬底的半导体晶片的顶部上制造器件层。 器件层包括有源器件。 该方法还包括在处理晶片的顶部形成富含阱的层。 成形包括蚀刻处理晶片的顶部部分，以在构造陷阱富集层的手柄晶片的顶部部分中形成结构。 该方法还包括将手柄晶片的顶表面接合到半导体晶片的顶表面。 该方法还包括去除半导体晶片的底部衬底部分。

公开(公告)号：US09515139B2

公开(公告)日：2016-12-06

申请号：US14746398

申请日：2015-06-22

Applicant: QUALCOMM Incorporated

Inventor： Anton Arriagada ,  Michael A. Stuber ,  Stuart B. Molin

IPC: H01L21/30 ,  H01L29/06 ,  H01L21/02 ,  H01L21/20 ,  H01L21/84 ,  H01L29/78 ,  H01L27/12 ,  H01L21/268 ,  H01L21/304 ,  H01L21/306 ,  H01L21/762

CPC classification number: H01L29/0692 ,  H01L21/02365 ,  H01L21/2007 ,  H01L21/268 ,  H01L21/304 ,  H01L21/30604 ,  H01L21/76243 ,  H01L21/76251 ,  H01L21/7806 ,  H01L21/84 ,  H01L25/00 ,  H01L27/1203 ,  H01L29/7803

Abstract: A trap rich layer for an integrated circuit chip is formed by chemical etching and/or laser texturing of a surface of a semiconductor layer. In some embodiments, a trap rich layer is formed by a technique selected from the group of techniques consisting of laser texturing, chemical etch, irradiation, nanocavity formation, porous Si-etch, semi-insulating polysilicon, thermal stress relief and mechanical texturing. Additionally, combinations of two or more of these techniques may be used to form a trap rich layer.

公开(公告)号：US20190386026A1

公开(公告)日：2019-12-19

申请号：US16553362

申请日：2019-08-28

Applicant: QUALCOMM INCORPORATED

Inventor： Stuart B. Molin ,  Michael A. Stuber

IPC: H01L27/12 ,  H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L21/84 ,  H01L21/8234 ,  H01L27/082 ,  H01L27/088 ,  H01L29/06 ,  H01L29/732 ,  H01L29/739 ,  H01L29/744 ,  H01L21/683

Abstract: A vertical semiconductor device (e.g. a vertical power device, an IGBT device, a vertical bipolar transistor, a UMOS device or a GTO thyristor) is formed with an active semiconductor region, within which a plurality of semiconductor structures have been fabricated to form an active device, and below which at least a portion of a substrate material has been removed to isolate the active device, to expose at least one of the semiconductor structures for bottom side electrical connection and to enhance thermal dissipation. At least one of the semiconductor structures is preferably contacted by an electrode at the bottom side of the active semiconductor region.

公开(公告)号：US09783414B2

公开(公告)日：2017-10-10

申请号：US15386014

申请日：2016-12-21

Applicant: QUALCOMM INCORPORATED

Inventor： Michael A. Stuber

IPC: H01L21/00 ,  B81C1/00 ,  B81B3/00

CPC classification number: B81C1/00158 ,  B81B3/0021 ,  B81B7/008 ,  B81B2203/0127 ,  B81C1/00269 ,  B81C2201/0194 ,  B81C2203/037 ,  H01L21/2007 ,  H01L21/76256 ,  H01L21/76898 ,  H01L21/7806 ,  H01L21/84 ,  H01L23/481 ,  H01L25/00 ,  H01L27/1203 ,  H01L29/7803 ,  H01L2924/0002 ,  H01L2924/1461 ,  H01L2224/9202 ,  H01L2924/00

Abstract: A semiconductor wafer is formed with a first device layer having active devices. A handle wafer having a trap rich layer is bonded to a top surface of the semiconductor wafer. A second device layer having a MEMS device or acoustic filter device is formed on a bottom surface of the semiconductor wafer. The second device layer is formed either by monolithic fabrication processes or layer-transfer processes.