公开(公告)号：US10349513B2

公开(公告)日：2019-07-09

申请号：US15659187

申请日：2017-07-25

Applicant: QUALCOMM Incorporated

Inventor： Priyatharshan Pathmanathan

IPC: H05K1/02 ,  H01L23/522 ,  H01L23/528 ,  G06F13/40

Abstract: A system includes: a printed circuit board having a plurality of conductive traces; a processing device coupled to the printed circuit board and in electrical communication with the plurality of conductive traces; a first memory module and a second memory module in electrical communication with the plurality of conductive traces and sharing channels of the conductive traces, wherein the first memory module is physically more proximate to the processing device than is the second memory module; and an electronic band gap (EBG) structure physically disposed in an area between the first memory module and the second memory module.

公开(公告)号：US09722012B1

公开(公告)日：2017-08-01

申请号：US15255412

申请日：2016-09-02

Applicant: QUALCOMM Incorporated

Inventor： Priyatharshan Pathmanathan ,  Devarshi Patel ,  Dennis Allen Northgrave ,  Kyle Roberts

IPC: G11C11/40 ,  G11C11/24 ,  H01L49/02 ,  H01L23/498 ,  H01L27/108 ,  G11C11/401

CPC classification number: H01L28/40 ,  G11C7/02 ,  G11C11/401 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/00 ,  H01L27/108 ,  H01L28/00 ,  H05K1/0216 ,  H05K1/0228 ,  H05K1/116 ,  H05K1/162 ,  H05K2201/09636

Abstract: An electrical device including a structure having a plurality of dielectric layers, the structure further having a plurality of vertical electrical connections extending from a top layer of the dielectric layers to a bottom layer of the dielectric layers, a first vertical electrical connection of the plurality of vertical electrical connections including a first capacitive structure that extends in a plane perpendicular to a vertical dimension of the vertical electrical connection, wherein the first capacitive structure is disposed on a first dielectric layer of the plurality of dielectric layers, wherein the first dielectric layer is below the top layer, and a second vertical electrical connection of the plurality of vertical electrical connections including a second capacitive structure extending in the plane and disposed on the first dielectric layer.

公开(公告)号：US20180035533A1

公开(公告)日：2018-02-01

申请号：US15659187

申请日：2017-07-25

Applicant: QUALCOMM Incorporated

Inventor： Priyatharshan Pathmanathan

IPC: H05K1/02 ,  H01L23/522 ,  H01L23/528

CPC classification number: H05K1/0236 ,  G06F13/4086 ,  H01L23/5227 ,  H01L23/5286 ,  H05K1/0213 ,  H05K1/0225 ,  H05K1/025 ,  H05K1/0253 ,  H05K1/0298 ,  H05K2201/029 ,  H05K2201/09727 ,  H05K2201/10159

Abstract: A system includes: a printed circuit board having a plurality of conductive traces; a processing device coupled to the printed circuit board and in electrical communication with the plurality of conductive traces; a first memory module and a second memory module in electrical communication with the plurality of conductive traces and sharing channels of the conductive traces, wherein the first memory module is physically more proximate to the processing device than is the second memory module; and an electronic band gap (EBG) structure physically disposed in an area between the first memory module and the second memory module.

公开(公告)号：US09214426B1

公开(公告)日：2015-12-15

申请号：US14329889

申请日：2014-07-11

Applicant: QUALCOMM Incorporated

Inventor： Siamak Fazelpour ,  Priyatharshan Pathmanathan ,  John Stephen Loffink

IPC: H01L23/00 ,  H01L23/522 ,  H01L49/02

CPC classification number: H01L23/5227 ,  H01L23/645 ,  H01L24/02 ,  H01L24/13 ,  H01L28/10 ,  H01L2224/02373 ,  H01L2224/13012 ,  H01L2224/13024 ,  H01L2224/131 ,  H01L2924/1206 ,  H01L2924/19042 ,  H01L2924/00012 ,  H01L2924/014

Abstract: Methods and apparatuses for reducing excess on die capacitance. The method couples a first die pad to a first via. The method couples a second die pad to a second via. The method couples a first inductor to the first die pad and the second via. The method couples a second inductor to the second die pad and the first via.

Abstract translation: 减少裸片电容过剩的方法和装置。 该方法将第一管芯焊盘耦合到第一通孔。 该方法将第二管芯焊盘耦合到第二通孔。 该方法将第一电感器耦合到第一管芯焊盘和第二通孔。 该方法将第二电感器耦合到第二管芯焊盘和第一通孔。