公开(公告)号：US10453731B2

公开(公告)日：2019-10-22

申请号：US15331149

申请日：2016-10-21

Applicant: Raytheon Company

Inventor： John J. Drab

IPC: H01L27/14 ,  H01L21/683 ,  B24B37/20 ,  H01L23/00 ,  H01L27/146

Abstract: A method of transferring an integrated circuit (IC) onto an alternative substrate is provided at a wafer level to enable coefficient of thermal expansion (CTE) matching for a circuit layer to a different material. The method is executable relative to a wafer with a circuit layer, a first major surface, a second major surface opposite the first major surface, and a substrate affixed to the first major surface. The method includes temporarily bonding a handle to the second major surface, removing a majority of the substrate to expose the first major surface and bonding a second substrate to the first major surface with deposited bonding material.

公开(公告)号：US20190221547A1

公开(公告)日：2019-07-18

申请号：US16363356

申请日：2019-03-25

Applicant: Raytheon Company

Inventor： John J. Drab ,  Jason G. Milne

IPC: H01L25/065 ,  H01L21/78 ,  H01L21/56 ,  H01L23/31 ,  H01L21/50 ,  H01L23/10 ,  H01L21/54 ,  H01L23/00 ,  H01L25/00

Abstract: Structures and methods of fabricating semiconductor wafer assemblies that encapsulate one or die in a cavity etched into an oxide bonded semiconductor wafer stack. The methods generally include the steps of positioning the die in the cavity, mechanically and electrically mounting the die to the wafer stack, and encapsulating the die within the cavity by bonding a lid wafer to the wafer stack in one of multiple ways. Semiconductor processing steps are applied to construct the assemblies (e.g., deposition, annealing, chemical and mechanical polishing, etching, etc.) and connecting the die (e.g., bump bonding, wire interconnecting, ultrasonic bonding, oxide bonding, etc.) according to the embodiments described above.

公开(公告)号：US10354975B2

公开(公告)日：2019-07-16

申请号：US15156087

申请日：2016-05-16

Applicant: Raytheon Company

Inventor： Edward R. Soares ,  John J. Drab

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/58 ,  H01L25/00 ,  H01L27/06 ,  H01L21/027 ,  H01L21/768 ,  H01L21/822 ,  H01L25/065 ,  H01L23/66 ,  H01L21/66

Abstract: An electronic device integration method and integrated electronic device. The integration method may include the steps of preparing a first electronic device by forming an electrically conductive trace overlying a substrate, forming a barrier layer overlying the electrically conductive trace, forming one or more electrically conductive interconnects on the barrier layer, and forming a bonding layer overlying the trace and/or at least partially surrounding the one or more interconnects. The barrier layer is configured to prevent formation of an intermetallic compound between the trace and interconnect structures, while still enabling electrical communication between the trace and interconnect. The integration method may further include the steps of direct bonding the first electronic device to a second electronic device, direct bonding a third electronic device to the second electronic device, and so on. A high-temperature treatment and functional testing of the vertically integrated electronic device may be conducted after each stack sequence.

公开(公告)号：US10242967B2

公开(公告)日：2019-03-26

申请号：US15596663

申请日：2017-05-16

Applicant: Raytheon Company

Inventor： John J. Drab ,  Jason G. Milne

IPC: H01L21/50 ,  H01L21/54 ,  H01L21/78 ,  H01L23/10 ,  H01L25/00 ,  H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

Abstract: Structures and methods of fabricating semiconductor wafer assemblies that encapsulate one or die in a cavity etched into an oxide bonded semiconductor wafer stack. The methods generally include the steps of positioning the die in the cavity, mechanically and electrically mounting the die to the wafer stack, and encapsulating the die within the cavity by bonding a lid wafer to the wafer stack in one of multiple ways. Semiconductor processing steps are applied to construct the assemblies (e.g., deposition, annealing, chemical and mechanical polishing, etching, etc.) and connecting the die (e.g., bump bonding, wire interconnecting, ultrasonic bonding, oxide bonding, etc.) according to the embodiments described above.

公开(公告)号：US10128297B2

公开(公告)日：2018-11-13

申请号：US14947575

申请日：2015-11-20

Applicant: Raytheon Company

Inventor： John J. Drab ,  Justin Gordon Adams Wehner ,  Christian M. Boemler

IPC: H01L31/105 ,  H01L27/146 ,  H01L29/868 ,  H01L27/144

Abstract: A semiconductor structure having: a silicon structure; and a plurality of laterally spaced PiN diodes formed in the silicon structure; and a surface of the silicon structure configured to reduce reverse bias leakage current through the PiN diodes. In one embodiment, a gate electrode structures is disposed on a surface of the silicon structure, the gate electrode structure having portions disposed between adjacent pairs of the diodes, the gate structure being biased to prevent leakage current through the diodes.

公开(公告)号：US20150035014A1

公开(公告)日：2015-02-05

申请号：US13959081

申请日：2013-08-05

Applicant: Raytheon Company

Inventor： John J. Drab ,  Justin Gordon Adams Wehner ,  Christian M. Boemler

IPC: H01L27/146 ,  H01L29/868

CPC classification number: H01L27/14643 ,  H01L27/1446 ,  H01L27/14605 ,  H01L27/14649 ,  H01L27/14689 ,  H01L29/868 ,  H01L31/105

Abstract: A semiconductor structure having: a silicon structure; and a plurality of laterally spaced PiN diodes formed in the silicon structure; and a surface of the silicon structure configured to reduce reverse bias leakage current through the PiN diodes. In one embodiment, a gate electrode structures is disposed on a surface of the silicon structure, the gate electrode structure having portions disposed between adjacent pairs of the diodes, the gate structure being biased to prevent leakage current through the diodes.

Abstract translation: 一种半导体结构，具有：硅结构; 以及形成在所述硅结构中的多个横向间隔开的PiN二极管; 并且所述硅结构的表面被配置为减少穿过所述PiN二极管的反向偏置漏电流。 在一个实施例中，栅极电极结构设置在硅结构的表面上，栅极电极结构具有设置在相邻的二极管对之间的部分，栅极结构被偏置以防止通过二极管的漏电流。

公开(公告)号：US20220239383A1

公开(公告)日：2022-07-28

申请号：US17157377

申请日：2021-01-25

Applicant: Raytheon Company

Inventor： Matthew C. Thomas ,  John J. Drab ,  Theodore Mark Kellum

IPC: H04B10/80 ,  G02F1/295

Abstract: A communication system includes an antenna assembly. The antenna assembly includes an optical communication layer including a plurality of electro-optical (EO) antennas for communicating via an EO signal and a radio-frequency communication layer including a plurality of radio frequency (RF) antennas for communicating via an RF signal. A processor operates the antenna assembly to communicate via one or both of the EO signal and the RF signal.

公开(公告)号：US20190267353A1

公开(公告)日：2019-08-29

申请号：US16408902

申请日：2019-05-10

Applicant: Raytheon Company

Inventor： Edward R. Soares ,  John J. Drab

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/58 ,  H01L27/06 ,  H01L25/00 ,  H01L23/66 ,  H01L23/00 ,  H01L21/027

Abstract: An electronic device integration method and integrated electronic device. The integration method may include the steps of preparing a first electronic device by forming an electrically conductive trace overlying a substrate, forming a barrier layer overlying the electrically conductive trace, forming one or more electrically conductive interconnects on the barrier layer, and forming a bonding layer overlying the trace and/or at least partially surrounding the one or more interconnects. The barrier layer is configured to prevent formation of an intermetallic compound between the trace and interconnect structures, while still enabling electrical communication between the trace and interconnect. The integration method may further include the steps of direct bonding the first electronic device to a second electronic device, direct bonding a third electronic device to the second electronic device, and so on. A high-temperature treatment and functional testing of the vertically integrated electronic device may be conducted after each stack sequence.

公开(公告)号：US20190259653A1

公开(公告)日：2019-08-22

申请号：US16403317

申请日：2019-05-03

Applicant: RAYTHEON COMPANY

Inventor： Mary A. Teshiba ,  John J. Drab

IPC: H01L21/762 ,  H01L21/20

Abstract: A foundry-agnostic post-processing method for a wafer is provided. The wafer includes an active surface, a substrate and an intermediate layer interposed between the active surface and the substrate. The method includes removing the wafer from an output yield of a wafer processing foundry, thinning the substrate to the intermediate layer or within microns of the intermediate layer to expose a new surface and bonding the new surface to an alternate material substrate which provides for enhanced device performance as compared to the substrate.

公开(公告)号：US09887195B1

公开(公告)日：2018-02-06

申请号：US15297803

申请日：2016-10-19

Applicant: Raytheon Company

Inventor： John J. Drab ,  Mary A. Teshiba

IPC: H01L23/66 ,  H01L27/092 ,  H01L29/06 ,  H01L27/12 ,  H01L29/16 ,  H01L27/06

CPC classification number: H01L27/092 ,  H01L21/76898 ,  H01L21/84 ,  H01L23/481 ,  H01L23/66 ,  H01L25/065 ,  H01L27/0688 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/16 ,  H01L2223/6622

Abstract: A semiconductor, silicon-on-oxide (SOI) structure having a silicon layer disposed on a bottom oxide (BOX) insulating layer. A deep trench isolation (DTI) material passes vertically through the silicon layer to the bottom oxide insulating layer. The deep trench isolation material has a lower permittivity than the permittivity of the silicon. A coaxial transmission line having an inner electrical conductor and an outer electrically conductive shield structure disposed around the inner electrical conductor passing vertically through the deep trench isolation material to electrically connect electrical conductors disposed over the bottom oxide insulating layer to electrical conductors disposed under the contacts bottom oxide insulating layer.