公开(公告)号：US12001557B2

公开(公告)日：2024-06-04

申请号：US17125208

申请日：2020-12-17

Applicant: RENESAS ELECTRONICS AMERICA INC.

Inventor： Taimour Wehbe ,  Marc Adas

IPC: G06F21/57 ,  H04L9/32

CPC classification number: G06F21/57 ,  G06F2221/034 ,  H04L9/3236

Abstract: Example implementations include a method of requesting an instruction block associated with one or more instructions and located at one or more addresses of a system memory, obtaining the instruction block from the system memory, generating a hash of the instruction block, obtaining an expected hash associated with the instruction block, comparing the expected hash with the generated hash, in accordance with a determination that the expected hash matches the generated hash, generating a first validation response associated with the instruction block. Example implementations also include a method of obtaining a secure instruction image including an expected hash associated with an instruction block, the instruction block associated with one or more instructions and located at one or more addresses of a system memory, storing the secure instruction image at a configuration register, and enabling the hardware controller to perform one or more hashing operations associated with the instruction block during runtime of a system processor.

公开(公告)号：US20210200873A1

公开(公告)日：2021-07-01

申请号：US17125208

申请日：2020-12-17

Applicant: RENESAS ELECTRONICS AMERICA INC.

Inventor： Taimour Wehbe ,  Marc Adas

IPC: G06F21/57

Abstract: Example implementations include a method of requesting an instruction block associated with one or more instructions and located at one or more addresses of a system memory, obtaining the instruction block from the system memory, generating a hash of the instruction block, obtaining an expected hash associated with the instruction block, comparing the expected hash with the generated hash, in accordance with a determination that the expected hash matches the generated hash, generating a first validation response associated with the instruction block. Example implementations also include a method of obtaining a secure instruction image including an expected hash associated with an instruction block, the instruction block associated with one or more instructions and located at one or more addresses of a system memory, storing the secure instruction image at a configuration register, and enabling the hardware controller to perform one or more hashing operations associated with the instruction block during runtime of a system processor.