公开(公告)号：US10249560B2

公开(公告)日：2019-04-02

申请号：US15657689

申请日：2017-07-24

Applicant: Renesas Electronics Corporation

Inventor： Takafumi Betsui

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/50 ,  H01L23/538

Abstract: The object is to suppress rupture of the soldering balls when an atmosphere varying from a high temperature to a low temperature is repeated. A semiconductor device includes a semiconductor integrated circuit and a substrate. The semiconductor integrated circuit is, for example, a semiconductor chip. The coefficient of thermal expansion is different between the semiconductor integrated circuit and the substrate. The substrate includes a plurality of soldering balls on the opposite surface to the surface where the semiconductor integrated circuit is mounted. The substrate does not have the soldering balls at a position corresponding to at least one side of the fringe of the semiconductor integrated circuit.

公开(公告)号：US10043755B2

公开(公告)日：2018-08-07

申请号：US15552774

申请日：2015-06-26

Applicant: Renesas Electronics Corporation

Inventor： Takafumi Betsui ,  Motoo Suwa

IPC: H05K1/18 ,  H01L23/538 ,  H01L23/50 ,  H01L27/118

Abstract: An electronic device includes a first wiring substrate and a semiconductor device mounted on the first wiring substrate. The semiconductor device includes a second wiring substrate having a plurality of terminals, a plurality of first semiconductor chips mounted on the second wiring substrate, and a second semiconductor chip mounted on the second wiring substrate. The first wiring substrate includes a first power supply line and a second power supply line supplying a plurality of power supply potentials, whose types are different from each other, to the second semiconductor chip. In a plan view, the second power supply line is arranged to cross over a first substrate side of the second wiring substrate and a first chip side of the second semiconductor chip. In a plan view, the first power supply line is arranged to pass between the second power supply line and a part of the plurality of first semiconductor chips and to extend toward a region overlapping with the second semiconductor chip. An area of a region of the first power supply line, the region overlapping with the second power supply line in a thickness direction, is smaller than an area of another region of the first power supply line, the another region not overlapping with the second power supply line.

公开(公告)号：US12015020B2

公开(公告)日：2024-06-18

申请号：US18351777

申请日：2023-07-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takafumi Betsui

IPC: H01L23/538 ,  H01L25/16 ,  H02M3/155 ,  H02M1/44

CPC classification number: H01L25/16 ,  H01L23/5384 ,  H01L23/5386 ,  H02M3/155 ,  H02M1/44

Abstract: Semiconductor device has a regulator circuit having an even number of switching regulators that generate output power from an input power supply and a power management IC that controls the output potential generated by the switching regulator. semiconductor device is characterized in that a group of half of the even number of switching regulators is arranged on a first surface of semiconductor device system board, and a group of switching regulators, which is the remaining half, is arranged on a second surface that is in front-back relation with the first surface. This semiconductor device reduces semiconductor device board-area (pattern-resource).

公开(公告)号：US10123426B2

公开(公告)日：2018-11-06

申请号：US15792634

申请日：2017-10-24

Applicant: Renesas Electronics Corporation

Inventor： Takafumi Betsui

IPC: H05K1/18 ,  H01L23/495 ,  H05K3/30 ,  H05K3/46 ,  H05K1/02

Abstract: A semiconductor integrated circuit device includes a component built-in board in which at least a first core layer on which a first electronic component is mounted, a second core layer on which a second electronic component is mounted, an adhesive layer arranged between the first core layer and the second core layer, and wiring layers are stacked; a third electronic component mounted in a first core layer side of the component built-in board and electrically connected to the at least one of the first and second electronic components through the wiring layers; and an external connection terminal formed in a second core layer side of the component built-in board and electrically connected to at least one of the first and second electronic components.

公开(公告)号：US09818715B2

公开(公告)日：2017-11-14

申请号：US14523862

申请日：2014-10-25

Applicant: Renesas Electronics Corporation

Inventor： Jun Yamada ,  Takafumi Betsui

IPC: H05K7/10 ,  H05K7/12 ,  H01L23/00 ,  H01L23/538 ,  H01L23/14 ,  H01L23/31 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H05K3/32

CPC classification number: H01L24/33 ,  H01L23/145 ,  H01L23/31 ,  H01L23/3128 ,  H01L23/481 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49894 ,  H01L23/5383 ,  H01L23/5384 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/065 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05009 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/05124 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05568 ,  H01L2224/0557 ,  H01L2224/05572 ,  H01L2224/05573 ,  H01L2224/05611 ,  H01L2224/05624 ,  H01L2224/13009 ,  H01L2224/13147 ,  H01L2224/1329 ,  H01L2224/133 ,  H01L2224/13564 ,  H01L2224/13565 ,  H01L2224/13578 ,  H01L2224/13611 ,  H01L2224/13686 ,  H01L2224/16146 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/335 ,  H01L2224/33515 ,  H01L2224/45124 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/45164 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/73207 ,  H01L2224/73215 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2924/13091 ,  H01L2924/15333 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/181 ,  H05K3/323 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/04941

Abstract: A semiconductor integrated circuit chip, in which multi-core processors are integrated, is usually mounted over an organic wiring board by FC bonding to form a BGA package by being integrated with the substrate. In such a structure, power consumption is increased, and hence the power supplied only from a peripheral portion of the chip is insufficient, so that a power supply pad is also provided in the chip central portion. However, because of an increase in the wiring associated with the integration of a plurality of CPU cores, etc., there occurs a portion between the peripheral portion and the central portion of the chip, where a power supply pad cannot be arranged. According to the outline of the present application, in a semiconductor integrated circuit device such as a BGA, etc., in which a semiconductor chip is mounted over an interposer, such as a multilayer organic wiring board, in a face-up manner, a first group of metal through electrodes, which are provided in the semiconductor chip to supply a power supply potential to a core circuit, etc., and a first metal land over the interposer are interconnected by a first conductive adhesive member film.

公开(公告)号：US09190378B2

公开(公告)日：2015-11-17

申请号：US14294978

申请日：2014-06-03

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takashi Abematsu ,  Takafumi Betsui ,  Atsushi Kuroda

IPC: H01L23/52 ,  H01L23/00 ,  H01L23/498 ,  H01L23/12 ,  H01L25/065 ,  H01L23/04 ,  H01L21/56

CPC classification number: H01L24/17 ,  H01L21/563 ,  H01L23/04 ,  H01L23/12 ,  H01L23/49816 ,  H01L23/49838 ,  H01L24/73 ,  H01L25/0657 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/48464 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06558 ,  H01L2924/15311 ,  H01L2924/00012

Abstract: Provided is a semiconductor chip that is flip-chip mounted where an inner chip pad array and an outer chip pad array, which are arranged on an inner side and an outer side of IO cells in a staggered manner, are arranged to be spaced away from each other by a predetermined gap or greater. The predetermined gap represents a gap where one via can be arranged between an inner substrate pad array and an outer substrate pad array on a substrate which faces and is connected to the inner chip pad array and the outer chip pad array. In addition, the predetermined gap represents a gap where a plated wire is interconnected and then a resist opening for etch-back can be formed. Even in a case where a space for forming an interconnection is not present between outer substrate pad arrays, interconnection characteristics of the substrate are improved.

Abstract translation: 提供了一种倒装芯片，其中以交错方式布置在IO单元的内侧和外侧的内芯片焊盘阵列和外芯片焊盘阵列被布置成与 彼此相隔预定间隙或更大。 预定间隙表示一个间隙，其中一个通孔可以布置在衬底上的内部衬底焊盘阵列和外部衬底焊盘阵列之间，该衬底面对并连接到内部芯片焊盘阵列和外部芯片焊盘阵列。 此外，预定间隙表示电镀线互连的间隙，然后可以形成用于蚀刻的抗蚀剂开口。 即使在外基板焊盘阵列之间不存在用于形成互连的空间的情况下，也提高了基板的互连特性。

公开(公告)号：US11742336B2

公开(公告)日：2023-08-29

申请号：US17030712

申请日：2020-09-24

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takafumi Betsui

IPC: H01L23/538 ,  H01L25/16 ,  H02M3/155 ,  H02M1/44

CPC classification number: H01L25/16 ,  H01L23/5384 ,  H01L23/5386 ,  H02M3/155 ,  H02M1/44

Abstract: Semiconductor device has a regulator circuit having an even number of switching regulators that generate output power from an input power supply and a power management IC that controls the output potential generated by the switching regulator. semiconductor device is characterized in that a group of half of the even number of switching regulators is arranged on a first surface of semiconductor device system board, and a group of switching regulators, which is the remaining half, is arranged on a second surface that is in front-back relation with the first surface. This semiconductor device reduces semiconductor device board-area (pattern-resource).

公开(公告)号：US10726878B2

公开(公告)日：2020-07-28

申请号：US16010770

申请日：2018-06-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takafumi Betsui ,  Naoto Taoka ,  Motoo Suwa ,  Shigezumi Matsui ,  Norihiko Sugita ,  Yoshiharu Fukushima

IPC: G11C5/04 ,  H01L25/18 ,  H01L23/00 ,  H01L23/498 ,  G11C5/06 ,  H05K1/18 ,  H05K3/46 ,  H05K1/02 ,  G11C5/02

Abstract: A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.

公开(公告)号：US10103100B2

公开(公告)日：2018-10-16

申请号：US15163647

申请日：2016-05-24

Applicant: Renesas Electronics Corporation

Inventor： Takafumi Betsui ,  Nobuyuki Morikoshi ,  Tetsushi Hada

IPC: G06F13/42 ,  H01L23/522 ,  H01L23/00 ,  H01L23/498 ,  G06F1/32 ,  H01R13/645 ,  G06F13/38 ,  H01R24/58

Abstract: The semiconductor device has a semiconductor chip having a first-signal-output circuit operating at a first-power-supply voltage, a second-signal-output circuit operating at a second power supply voltage, and a plurality of bump electrodes; and a wiring board including a first main surface facing the main surface of the semiconductor chip, a second main surface opposite to the first main surface with a wiring layer therebetween, first external terminals on the first main surface, and second ones on the second main surface; the former being mounted on the latter to couple the bump electrodes to the first external terminals. When viewed from the second main surface, second external terminals to be supplied with the first signal and the second signal are arranged closer to the semiconductor chip than second external terminals to be supplied with the first power supply voltage and the second power supply voltage.

公开(公告)号：US09558806B1

公开(公告)日：2017-01-31

申请号：US15170535

申请日：2016-06-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Motoo Suwa ,  Takafumi Betsui ,  Masato Suzuki

IPC: G11C5/02 ,  G11C11/408 ,  H01L23/498 ,  H01L25/065 ,  H01L23/522 ,  H01L23/528 ,  G11C5/06

CPC classification number: G11C5/063 ,  G11C5/025 ,  G11C11/4082 ,  G11C11/4093 ,  G11C2207/105 ,  H01L23/5228 ,  H01L23/5283 ,  H01L23/5386 ,  H01L23/647 ,  H01L25/0655 ,  H01L2224/16227 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: The number of terminals included in a semiconductor device which is included in an electronic device is reduced. The electronic device includes: a first semiconductor device having first and second input terminals; a second semiconductor device having a first output terminal and a first driver circuit to drive the first output terminal; and a wiring substrate over which the first and second semiconductor devices are mounted. The first and second input terminals are commonly coupled to the first output terminal via a first line formed on the wiring substrate. A composite resistance value of first and second termination resistors coupled to the first and second input terminals, respectively, is equivalent to a drive impedance of the first driver circuit.

Abstract translation: 包括在包括在电子设备中的半导体器件中的终端的数量减少。 电子设备包括：具有第一和第二输入端的第一半导体器件; 具有第一输出端和驱动所述第一输出端的第一驱动电路的第二半导体器件; 以及安装有第一和第二半导体器件的布线基板。 第一和第二输入端通常经由形成在布线基板上的第一线耦合到第一输出端。 分别耦合到第一和第二输入端的第一和第二终端电阻的复合电阻值等于第一驱动电路的驱动阻抗。