Abstract:
This disclosure relates to integrated circuit (IC) packages and methods of manufacturing the same. In one method, a printed circuit board is provided with semiconductor die. The semiconductor die includes a Back-End-of-Line (BEOL) region, a Front-End-of-Line (FEOL) region, and a semiconductor handle such that the BEOL region, the FEOL region, and the semiconductor handle are stacked. A first polymer layer is provided over the printed circuit board so as to cover the semiconductor die. The semiconductor handle of the semiconductor die is exposed through the first polymer layer and removed. A second polymer layer is then provided so that the BEOL region, the FEOL region, and at least a portion of the second polymer layer are stacked. The second polymer layer may be provided to have high thermal conductivity and electric isolation properties thereby providing advantageous package characteristics.
Abstract:
A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned die attached to the printed circuit substrate. The thinned die includes at least one device layer over the printed circuit substrate and at least one deep well within the at least one device layer. A protective layer is disposed over the at least one deep well, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 106 Ohm-cm.
Abstract:
This disclosure relates to integrated circuit (IC) packages and methods of manufacturing the same. In one method, a printed circuit board is provided with semiconductor die. The semiconductor die includes a Back-End-of-Line (BEOL) region, a Front-End-of-Line (FEOL) region, and a semiconductor handle such that the BEOL region, the FEOL region, and the semiconductor handle are stacked. A first polymer layer is provided over the printed circuit board so as to cover the semiconductor die. The semiconductor handle of the semiconductor die is exposed through the first polymer layer and removed. A second polymer layer is then provided so that the BEOL region, the FEOL region, and at least a portion of the second polymer layer are stacked. The second polymer layer may be provided to have high thermal conductivity and electric isolation properties thereby providing advantageous package characteristics.
Abstract:
A printed circuit module and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned die attached to the printed circuit substrate. The thinned die includes at least one device layer over the printed circuit substrate and a buried oxide (BOX) layer over the at least one device layer. A polymer layer is disposed over the BOX layer, wherein the polymer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 103 Ohm-cm.
Abstract:
A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a polymer substrate and an interfacial layer over the polymer substrate. A buried oxide layer resides over the interfacial layer, and a device layer with at least a portion of a field effect device resides over the buried oxide layer. The polymer substrate is molded over the interfacial adhesion layer and has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity greater than 1012 Ohm-cm. Methods of manufacture for the semiconductor device include removing a wafer handle to expose a first surface of the buried oxide layer, disposing the interfacial adhesion layer onto the first surface of the buried oxide layer, and molding the polymer substrate onto the interfacial adhesion layer.
Abstract:
The present disclosure relates to radio frequency (RF) microelectromechanical system (MEMS) device packaging, and specifically to reducing harmonic distortion caused by such packaging. In one embodiment, a die is provided that employs a gold-doped silicon substrate, wherein at least one RF MEMS device is disposed on the gold-doped silicon substrate. By employing the gold-doped silicon substrate, the packaging can achieve an exceptionally high resistivity without any additional expensive components, wherein the high resistivity has an associated low carrier lifetime. Notably, the low carrier lifetime corresponds to reduced harmonic distortion generated by the gold-doped silicon substrate, even when operating at high power. Thus, the gold-doped silicon substrate provides a less expensive packaging in which to place RF MEMS devices, wherein the packaging is capable of operating at high power with reduced harmonic distortion.
Abstract:
Aspects disclosed in the detailed description include an antenna on a device assembly. A device assembly includes a silicon device layer having at least one antenna. The device assembly also includes a polymer substrate that is formed with insulating material that does not interfere with the at least one antenna in the silicon device layer. As a result, it is unnecessary to shield the at least one antenna from the polymer substrate, thus allowing radio frequency (RF) signals radiating from the at least one antenna to pass through the polymer substrate.
Abstract:
This disclosure relates to integrated circuit (IC) packages and methods of manufacturing the same. In one method, a printed circuit board is provided with semiconductor die. The semiconductor die includes a Back-End-of-Line (BEOL) region, a Front-End-of-Line (FEOL) region, and a semiconductor handle such that the BEOL region, the FEOL region, and the semiconductor handle are stacked. A first polymer layer is provided over the printed circuit board so as to cover the semiconductor die. The semiconductor handle of the semiconductor die is exposed through the first polymer layer and removed. A second polymer layer is then provided so that the BEOL region, the FEOL region, and at least a portion of the second polymer layer are stacked. The second polymer layer may be provided to have high thermal conductivity and electric isolation properties thereby providing advantageous package characteristics.
Abstract:
A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned die attached to the printed circuit substrate. The thinned die includes at least one device layer over the printed circuit substrate and at least one deep well within the at least one device layer. A protective layer is disposed over the at least one deep well, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 106 Ohm-cm.
Abstract:
A printed circuit module having a protective layer in place of a low-resistivity handle layer and methods for manufacturing the same are disclosed. The printed circuit module includes a printed circuit substrate with a thinned die attached to the printed circuit substrate. The thinned die includes at least one device layer over the printed circuit substrate and at least one deep well within the at least one device layer. A protective layer is disposed over the at least one deep well, wherein the protective layer has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity of greater than 106 Ohm-cm.