公开(公告)号：US12106893B2

公开(公告)日：2024-10-01

申请号：US17438868

申请日：2020-03-12

Applicant: ROHM CO., LTD.

Inventor： Akihito Saito ,  Isamu Nishimura ,  Yoshihiro Sekimoto

IPC: H01F41/04 ,  H01F5/00 ,  H01F5/06 ,  H01F41/12 ,  H04N23/54

CPC classification number: H01F41/041 ,  H01F5/003 ,  H01F5/06 ,  H01F41/127 ,  H04N23/54

Abstract: A coil module includes a conductor layer, at least one element, and a sealing resin. The conductor layer is formed along a predetermined plane and includes a wiring portion and a helical-shaped coil portion. The at least one element is mounted on the wiring portion. The sealing resin covers the conductor layer and the at least one element. The sealing resin is integrally formed of a single type of resin material and has a predetermined thickness in a first direction perpendicular to the plane.

公开(公告)号：US11315866B2

公开(公告)日：2022-04-26

申请号：US16893650

申请日：2020-06-05

Applicant: ROHM CO., LTD.

Inventor： Isamu Nishimura ,  Hirofumi Takeda ,  Hideaki Yanagida ,  Taro Hayashi ,  Natsuki Sakamoto

IPC: H01L29/40 ,  H01L23/498 ,  H01L23/48 ,  H01L21/48 ,  H01L23/00 ,  H01L43/04

Abstract: A semiconductor device includes: a substrate including a main surface; a wiring portion including a first conductive layer formed on the main surface, and a first plating layer which is provided on the first conductive layer and on which an oxide film is formed; a semiconductor element including an element mounting surface and an element electrode formed on the element mounting surface; a bonding portion including a second plating layer made of the same material as the first plating layer and laminated on the first conductive layer, and a solder layer laminated on the second plating layer and bonded to the element electrode; and a sealing resin covering the semiconductor element.

公开(公告)号：US10930574B2

公开(公告)日：2021-02-23

申请号：US16394505

申请日：2019-04-25

Applicant: Rohm Co., Ltd.

Inventor： Isamu Nishimura

IPC: H01L23/31 ,  H01L23/367 ,  H01L23/495 ,  H01L21/56

Abstract: A semiconductor device includes a semiconductor element, a first substrate, a first electrode, a second electrode and a sealing resin. The first substrate has a first front surface and a first back surface that are spaced apart from each other in a thickness direction. The semiconductor element is mounted on the first main surface. The first electrode includes a first conductive portion and a second conductive portion. The first conductive portion is formed on a portion of the first front surface. The second conductive portion is connected to the first conductive portion and overlaps with the first substrate as viewed in a first direction perpendicular to the thickness direction. The sealing resin covers the semiconductor element. The second electrode is exposed from the sealing resin and electrically connected to the first electrode. The second electrode is in contact with the second conductive portion.

公开(公告)号：US09660150B2

公开(公告)日：2017-05-23

申请号：US15139006

申请日：2016-04-26

Applicant: ROHM CO., LTD.

Inventor： Isamu Nishimura ,  Yasuhiro Fuwa

IPC: H01L33/00 ,  H01L33/50 ,  H01L33/32 ,  H01L33/60 ,  H01L33/62 ,  H01L33/56 ,  H05B33/08

CPC classification number: H01L33/502 ,  H01L25/167 ,  H01L33/32 ,  H01L33/56 ,  H01L33/60 ,  H01L33/62 ,  H01L2224/16225 ,  H01L2924/181 ,  H05B33/0803 ,  H05B33/0842 ,  H01L2924/00012

Abstract: A semiconductor light-emitting device includes a substrate, an LED chip, a control element, a conductive layer and an insulating layer. The substrate, made of a semiconductor material, has an obverse surface and a reverse surface spaced apart from each other in the thickness direction of the substrate. The control element controls light emission of the LED chip. The conductive layer is electrically connected to the LED chip and the control element. The insulating layer is arranged between at least apart of the conductive layer and the substrate. The substrate has a recess formed in the obverse surface, and the LED chip is housed in the recess. The control element is arranged between the LED chip and the reverse surface in the thickness direction of the substrate.

公开(公告)号：US11657953B2

公开(公告)日：2023-05-23

申请号：US17230356

申请日：2021-04-14

Applicant: ROHM CO., LTD.

Inventor： Kosei Osada ,  Isamu Nishimura ,  Tetsuya Kagawa ,  Daiki Yanagishima ,  Toshiyuki Ishikawa ,  Michihiko Mifuji ,  Satoshi Kageyama ,  Nobuyuki Kasahara

IPC: H01F27/28 ,  H01L23/64 ,  H01L23/522 ,  H01L23/58 ,  H01L23/495 ,  H01L23/31

CPC classification number: H01F27/288 ,  H01F27/2804 ,  H01L23/49575 ,  H01L23/5225 ,  H01L23/5227 ,  H01L23/585 ,  H01L23/645 ,  H01F2027/2819 ,  H01L23/3107 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/06135 ,  H01L2224/48137 ,  H01L2224/48195 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2224/49175 ,  H01L2924/10253 ,  H01L2924/10272 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19104

Abstract: The semiconductor device of the present invention includes an insulating layer, a high voltage coil and a low voltage coil which are disposed in the insulating layer at an interval in the vertical direction, a low potential portion which is provided in a low voltage region disposed around a high voltage region for the high voltage coil in planar view and is connected with potential lower than the high voltage coil, and an electric field shield portion which is disposed between the high voltage coil and the low voltage region and includes an electrically floated metal member.

公开(公告)号：US10985083B2

公开(公告)日：2021-04-20

申请号：US16269816

申请日：2019-02-07

Applicant: Rohm Co., Ltd.

Inventor： Isamu Nishimura

IPC: H01L23/49 ,  H01L21/56 ,  H01L23/373 ,  H01L23/31 ,  H01L21/288 ,  H01L23/498

Abstract: A semiconductor device includes a semiconductor element, a wiring portion, an electrode pad, a sealing resin and a heat dissipation layer. The semiconductor element has a front surface and a back surface opposite to the front surface in a thickness direction of the semiconductor device. The wiring portion is electrically connected to the semiconductor element. The electrode pad is electrically connected to the wiring portion. The sealing resin covers the semiconductor element. The heat dissipation layer is held in contact with the back surface of the semiconductor element and exposed from the sealing resin. The semiconductor element overlaps with the first heat dissipation layer as viewed in the thickness direction.

公开(公告)号：US10651374B2

公开(公告)日：2020-05-12

申请号：US16208544

申请日：2018-12-03

Applicant: ROHM CO., LTD.

Inventor： Isamu Nishimura ,  Hirofumi Takeda

IPC: H01L43/14 ,  H01L43/04 ,  H01L43/06

Abstract: A semiconductor device includes a substrate having a front surface and a mounting surface that are separate from each other in a thickness direction. The substrate is formed with a through-hole that penetrates through in the thickness direction. A semiconductor element is mounted on the front surface of the substrate, and a front-surface wire line is formed on the front surface of the substrate to be electrically connected to the semiconductor element. A column is provided inside the through-hole, and is electrically connected to the front-surface wiring line. An electrode pad is provided on the mounting surface of the substrate, and is electrically connected to the column. A resin-layer through portion is also provided inside the through-hole. The semiconductor element is covered with a sealing resin. The resin-layer through portion has an orthogonal surface in contact with the column. The orthogonal surface is orthogonal to the mounting surface.

公开(公告)号：US10070530B2

公开(公告)日：2018-09-04

申请号：US15646086

申请日：2017-07-10

Applicant: ROHM CO., LTD.

Inventor： Motohiro Toyonaga ,  Yasuhiro Fuwa ,  Mamoru Yamagami ,  Isamu Nishimura

IPC: H05K1/18 ,  H01L21/48 ,  H01L23/00 ,  H01L23/13 ,  H01L23/498 ,  H01L23/31 ,  H05K1/11 ,  H05K3/00 ,  H05K3/28 ,  H05K1/02

Abstract: An electronic component includes a substrate including a first principal surface, a second principal surface positioned on a side opposite to the first principal surface, a first side surface that connects the first principal surface and the second principal surface and that extends along a first direction, a second side surface that connects the first principal surface and the second principal surface and that extends along a second direction intersecting the first direction, and a corner portion that connects the first side surface and the second side surface and that has a curved surface curved outwardly, and a chip arranged at the first principal surface of the substrate.

公开(公告)号：US09627344B2

公开(公告)日：2017-04-18

申请号：US14243245

申请日：2014-04-02

Applicant: ROHM CO., LTD.

Inventor： Satoshi Kageyama ,  Isamu Nishimura

IPC: H01L23/00 ,  H01L23/495 ,  H01L23/532 ,  H01L23/31

CPC classification number: H01L24/45 ,  H01L23/3121 ,  H01L23/4952 ,  H01L23/49548 ,  H01L23/49582 ,  H01L23/53223 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L24/48 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/0347 ,  H01L2224/0382 ,  H01L2224/03906 ,  H01L2224/04026 ,  H01L2224/04042 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05164 ,  H01L2224/05166 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05655 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/48639 ,  H01L2224/48644 ,  H01L2224/48655 ,  H01L2224/48839 ,  H01L2224/48844 ,  H01L2224/48855 ,  H01L2224/73265 ,  H01L2224/83439 ,  H01L2924/181 ,  H01L2924/01204 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

Abstract: The semiconductor device of the present invention includes an insulating layer, a copper wiring for wire connection formed on the insulating layer, a shock absorbing layer formed on an upper surface of the copper wiring, the shock absorbing layer being made of a metallic material with a hardness higher than copper, a bonding layer formed on the shock absorbing layer, the bonding layer having a connection surface for a wire, and a side protecting layer covering a side surface of the copper wiring, wherein the side protecting layer has a thickness thinner than a distance from the upper surface of the copper wiring to the connection surface of the bonding layer.

公开(公告)号：US09257387B2

公开(公告)日：2016-02-09

申请号：US14824962

申请日：2015-08-12

Applicant: ROHM CO., LTD.

Inventor： Isamu Nishimura ,  Michihiko Mifuji ,  Kazumasa Nishio

IPC: H01L21/02 ,  H01L23/522 ,  H01L23/528 ,  H01L27/01 ,  H01L49/02

CPC classification number: H01L23/5228 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/7687 ,  H01L23/522 ,  H01L23/5223 ,  H01L23/5226 ,  H01L23/5258 ,  H01L23/528 ,  H01L23/53223 ,  H01L23/5329 ,  H01L27/016 ,  H01L28/24 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device has a resistor area and wiring area selectively disposed on a semiconductor substrate. In this semiconductor device, a second interlayer insulating film is formed above the semiconductor substrate, and a thin-film resistor is disposed on the second interlayer insulating film in the resistor area. Vias that contact the thin-film resistor from below are formed in the second interlayer insulating film. A wiring line is disposed on the second interlayer insulating film in the wiring area. A dummy wiring line that covers the thin-film resistor from above is disposed in a third wiring layer that is in the same layer as the wiring line, and an insulating film is interposed between the thin-film resistor and the dummy wiring line.